WM is a family of architectures that achieve significantly greater
performance than RISC designs -- often by a factor of four or more.
WM is a superscalar architecture; that is, it achieves its performance
by executing more than one instruction concurrently. Unlike other
superscalar designs, WM ameliorates the common problems encountered
in achieving sustained concurrent execution of instructions by unusual
approaches to the semantics of its basic instruction set. The resulting
charms of the design are the simplicity of the mechanisms used and
the synergy of their interaction; its modest demands on compiler
technology; its broad spectrum of applicability; and, most of all,
the fact that the complexity of an implementation is comparable to
that of RISC machines.
WM is a family of architectures in the sense that it is
parameterized by the size (width) of the arithmetic operations
supported by a member of the family. WM supports integer
arithmetic of width n-bits and floating point arithmetic of width
m-bits directly in hardware. Thus, for example, WM<16,0> is a
16-bit (integer only) microcomputer, while WM<64,64> is likely
to be a high performance machine with a large 64-bit virtual
address space and 64-bit floating point arithmetic.
The WM Team (it evolved a lot over time)
We're still working on gather all of the various WM papers.
Unfortunately, most of the reports are not available electronically.
If you would like to obtain a hardcopy of any of these, send mail
to firstname.lastname@example.org. We are
making postscript versions of preliminary drafts available via ftp
where possible, in the hopes that this might help you decide whether
you want to bother with hardcopies.
- Evaluation of the WM Architecture
Proc. 19th ISCA,
Gold Coast, Australia, May 1992, pages 382-390.
- The WM Protection Mechanism
P.M. Widener, G.S. Briercheck, S.C. Himmich,
S.A. McKee, R.V. Peri, Wm.A. Wulf
Technical Report CS-92-28, August 1992
- WM FIFOs: Size Analysis
Wm.A. Wulf, R.V. Wad
Technical Report CS-91-16, July 1991
- Code Generation for Streaming: An Access/Execute Mechanism
M.E. Benitez and J.W. Davidson
Proc. ASPLOS-IV, April 1991. Also Technical Report CS-90-23, December 1990.
- A Proposal for WM Interprocess Communication
Working paper, March 1991
- Implementation Independent Architectural Comparison
A.S. Grimshaw, D. Chisholm, B. Segal, M.E. Benitez, M.H. Salinas, P.Kester, S.T. McCalla
Technical Report CS-90-12, June 1990
- A VLSI Implementation of the Stream Control Unit for the WM Machine (sic)
Masters Thesis, University of Virginia, May 1990
- The WM Family of Computer Architectures (draft version)
Wm.A. Wulf and C. Hitchcock
Technical Report CS-90-05, March 1990
- An Implementation Independent Model of the WM Computer Architecture
Masters Thesis, University of Virginia, December 1989
- The WM Computer Architectures: Principles of Operation
Technical Report CS-89-09, October 1989 (updated January 1990)
- The WM Computer Architecture: Definition and Rationale (versions 1 and 2)
Technical Report CS-88-22, October 1988, revised February 1989