Document Title

00001 /*
00002  * alpha.h - Alpha ISA definitions
00003  *
00004  * This file is a part of the SimpleScalar tool suite written by
00005  * Todd M. Austin as a part of the Multiscalar Research Project.
00006  *  
00007  * The tool suite is currently maintained by Doug Burger and Todd M. Austin.
00008  * 
00009  * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Todd M. Austin
00010  *
00011  * This source file is distributed "as is" in the hope that it will be
00012  * useful.  The tool set comes with no warranty, and no author or
00013  * distributor accepts any responsibility for the consequences of its
00014  * use. 
00015  * 
00016  * Everyone is granted permission to copy, modify and redistribute
00017  * this tool set under the following conditions:
00018  * 
00019  *    This source code is distributed for non-commercial use only. 
00020  *    Please contact the maintainer for restrictions applying to 
00021  *    commercial use.
00022  *
00023  *    Permission is granted to anyone to make or distribute copies
00024  *    of this source code, either as received or modified, in any
00025  *    medium, provided that all copyright notices, permission and
00026  *    nonwarranty notices are preserved, and that the distributor
00027  *    grants the recipient permission for further redistribution as
00028  *    permitted by this document.
00029  *
00030  *    Permission is granted to distribute this file in compiled
00031  *    or executable form under the same conditions that apply for
00032  *    source code, provided that either:
00033  *
00034  *    A. it is accompanied by the corresponding machine-readable
00035  *       source code,
00036  *    B. it is accompanied by a written offer, with no time limit,
00037  *       to give anyone a machine-readable copy of the corresponding
00038  *       source code in return for reimbursement of the cost of
00039  *       distribution.  This written offer must permit verbatim
00040  *       duplication by anyone, or
00041  *    C. it is distributed by someone who received only the
00042  *       executable form, and is accompanied by a copy of the
00043  *       written offer of source code that they received concurrently.
00044  *
00045  * In other words, you are welcome to use, share and improve this
00046  * source file.  You are forbidden to forbid anyone else to use, share
00047  * and improve what you give them.
00048  *
00049  * INTERNET: dburger@cs.wisc.edu
00050  * US Mail:  1210 W. Dayton Street, Madison, WI 53706
00051  *
00052  * $Id: alpha.h,v 1.1.1.1 2000/05/26 15:22:27 taustin Exp $
00053  *
00054  * $Log: alpha.h,v $
00055  * Revision 1.1.1.1  2000/05/26 15:22:27  taustin
00056  * SimpleScalar Tool Set
00057  *
00058  *
00059  * Revision 1.4  1999/12/31 18:58:15  taustin
00060  * quad_t naming conflicts removed
00061  * MD_FETCH_INST() macro fixed
00062  * Alpha instruction set extensions (MVI, BWX, AMASK, IMPLVER, etc...)
00063  *
00064  * Revision 1.3  1999/12/13 18:59:40  taustin
00065  * cross endian execution support added
00066  *
00067  * Revision 1.2  1998/08/31 17:15:23  taustin
00068  * fixed non-portable SEXT definitions
00069  *
00070  * Revision 1.1  1998/08/27 16:53:36  taustin
00071  * Initial revision
00072  *
00073  * Revision 1.1  1998/05/06  01:09:18  calder
00074  * Initial revision
00075  *
00076  * Revision 1.5  1997/03/11  01:38:10  taustin
00077  * updated copyrights
00078  * long/int tweaks made for ALPHA target support
00079  * IFAIL() hook now allows simulators to declare instruction faults
00080  * IDIV()/IMOD()/FDIV() hooks now support simulator fault masking
00081  * supported added for non-GNU C compilers
00082  *
00083  * Revision 1.4  1997/01/06  16:08:10  taustin
00084  * comments updated
00085  * functional unit definitions moved from ss.def
00086  *
00087  * Revision 1.3  1996/12/27  15:55:37  taustin
00088  * fixed system header collision with MAXINT
00089  *
00090  * Revision 1.1  1996/12/05  18:50:23  taustin
00091  * Initial revision
00092  *
00093  */
00094 
00095 #ifndef ALPHA_H
00096 #define ALPHA_H
00097 
00098 #include <stdio.h>
00099 
00100 #include "host.h"
00101 #include "misc.h"
00102 #include "config.h"
00103 #include "endian.h"
00104 
00105 
00106 /*
00107  * This file contains various definitions needed to decode, disassemble, and
00108  * execute Alpha AXP instructions.
00109  */
00110 
00111 /* build for Alpha AXP target */
00112 #define TARGET_ALPHA
00113 
00114 /* probe cross-endian execution */
00115 #if defined(BYTES_BIG_ENDIAN)
00116 #define MD_CROSS_ENDIAN
00117 #endif
00118 
00119 /* not applicable/available, usable in most definition contexts */
00120 #define NA              0
00121 
00122 /*
00123  * target-dependent type definitions
00124  */
00125 
00126 /* define MD_QWORD_ADDRS if the target requires 64-bit (qword) addresses */
00127 #define MD_QWORD_ADDRS
00128 
00129 /* address type definition */
00130 typedef qword_t md_addr_t;
00131 
00132 
00133 /*
00134  * target-dependent memory module configuration
00135  */
00136 
00137 /* physical memory page size (must be a power-of-two) */
00138 #define MD_PAGE_SIZE            8192
00139 #define MD_LOG_PAGE_SIZE        13
00140 
00141 
00142 /*
00143  * target-dependent instruction faults
00144  */
00145 
00146 enum md_fault_type {
00147   md_fault_none = 0,            /* no fault */
00148   md_fault_access,              /* storage access fault */
00149   md_fault_alignment,           /* storage alignment fault */
00150   md_fault_overflow,            /* signed arithmetic overflow fault */
00151   md_fault_div0,                /* division by zero fault */
00152   md_fault_invalid,             /* invalid arithmetic operation */ 
00153                                 /* added to allow SQRT{S,T} in FIX exts */
00154   md_fault_break,               /* BREAK instruction fault */
00155   md_fault_unimpl,              /* unimplemented instruction fault */
00156   md_fault_internal             /* internal S/W fault */
00157 };
00158 
00159 
00160 /*
00161  * target-dependent register file definitions, used by regs.[hc]
00162  */
00163 
00164 /* number of integer registers */
00165 #define MD_NUM_IREGS            32
00166 
00167 /* number of floating point registers */
00168 #define MD_NUM_FREGS            32
00169 
00170 /* number of control registers */
00171 #define MD_NUM_CREGS            2
00172 
00173 /* total number of registers, excluding PC and NPC */
00174 #define MD_TOTAL_REGS                                                   \
00175   (/*int*/32 + /*fp*/32 + /*misc*/2 + /*tmp*/1 + /*mem*/1 + /*ctrl*/1)
00176 
00177 /* general purpose (integer) register file entry type */
00178 typedef qword_t md_gpr_t[MD_NUM_IREGS];
00179 
00180 /* floating point register file entry type */
00181 typedef union {
00182   qword_t q[MD_NUM_FREGS];      /* integer qword view */
00183   dfloat_t d[MD_NUM_FREGS];     /* double-precision floating point view */
00184 } md_fpr_t;
00185 
00186 /* control register file contents */
00187 typedef struct {
00188   qword_t fpcr;                 /* floating point condition codes */
00189   qword_t uniq;                 /* process-unique register */
00190 } md_ctrl_t;
00191 
00192 /* well known registers */
00193 enum md_reg_names {
00194   MD_REG_V0 = 0,        /* return value reg */
00195   MD_REG_ERR = 7,
00196   MD_REG_FP = 15,       /* frame pointer */
00197   MD_REG_A0 = 16,       /* argument regs */
00198   MD_REG_A1 = 17,
00199   MD_REG_A2 = 18,
00200   MD_REG_A3 = 19,
00201   MD_REG_A4 = 20,
00202   MD_REG_A5 = 21,
00203   MD_REG_RA = 26,       /* return address reg */
00204   MD_REG_GP = 29,       /* global data section pointer */
00205   MD_REG_SP = 30,       /* stack pointer */
00206   MD_REG_ZERO = 31      /* zero register */
00207 };
00208 
00209 
00210 /*
00211  * target-dependent instruction format definition
00212  */
00213 
00214 /* instruction formats */
00215 typedef word_t md_inst_t;
00216 
00217 /* preferred nop instruction definition */
00218 extern md_inst_t MD_NOP_INST;
00219 
00220 /* target swap support */
00221 #ifdef MD_CROSS_ENDIAN
00222 
00223 #define MD_SWAPH(X)             SWAP_HALF(X)
00224 #define MD_SWAPW(X)             SWAP_WORD(X)
00225 #define MD_SWAPQ(X)             SWAP_QWORD(X)
00226 #define MD_SWAPI(X)             SWAP_WORD(X)
00227 
00228 #else /* !MD_CROSS_ENDIAN */
00229 
00230 #define MD_SWAPH(X)             (X)
00231 #define MD_SWAPW(X)             (X)
00232 #define MD_SWAPQ(X)             (X)
00233 #define MD_SWAPD(X)             (X)
00234 #define MD_SWAPI(X)             (X)
00235 
00236 #endif
00237 
00238 /* fetch an instruction */
00239 #define MD_FETCH_INST(INST, MEM, PC)                                    \
00240   { (INST) = MEM_READ_WORD((MEM), (PC)); }
00241 
00242 /*
00243  * target-dependent loader module configuration
00244  */
00245 
00246 /* maximum size of argc+argv+envp environment */
00247 #define MD_MAX_ENVIRON          16384
00248 
00249 
00250 /*
00251  * machine.def specific definitions
00252  */
00253 
00254 /* inst -> enum md_opcode mapping, use this macro to decode insts */
00255 #define MD_TOP_OP(INST)         (((INST) >> 26) & 0x3f)
00256 #define MD_SET_OPCODE(OP, INST)                                         \
00257   { OP = md_mask2op[MD_TOP_OP(INST)];                                   \
00258     while (md_opmask[OP])                                               \
00259       OP = md_mask2op[((INST >> md_opshift[OP]) & md_opmask[OP])        \
00260                       + md_opoffset[OP]]; }
00261 
00262 /* largest opcode field value (currently upper 8-bit are used for pre/post-
00263     incr/decr operation specifiers */
00264 #define MD_MAX_MASK             2048
00265 
00266 /* internal decoder state */
00267 extern enum md_opcode md_mask2op[];
00268 extern unsigned int md_opoffset[];
00269 extern unsigned int md_opmask[];
00270 extern unsigned int md_opshift[];
00271 
00272 /* global opcode names, these are returned by the decoder (MD_OP_ENUM()) */
00273 enum md_opcode {
00274   OP_NA = 0,    /* NA */
00275 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) OP,
00276 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT) OP,
00277 #define CONNECT(OP)
00278 #include "machine.def"
00279   OP_MAX        /* number of opcodes + NA */
00280 };
00281 
00282 /* enum md_opcode -> description string */
00283 #define MD_OP_NAME(OP)          (md_op2name[OP])
00284 extern char *md_op2name[];
00285 
00286 /* enum md_opcode -> opcode operand format, used by disassembler */
00287 #define MD_OP_FORMAT(OP)        (md_op2format[OP])
00288 extern char *md_op2format[];
00289 
00290 /* function unit classes, update md_fu2name if you update this definition */
00291 enum md_fu_class {
00292   FUClamd_NA = 0,       /* inst does not use a functional unit */
00293   IntALU,               /* integer ALU */
00294   IntMULT,              /* integer multiplier */
00295   IntDIV,               /* integer divider */
00296   FloatADD,             /* floating point adder/subtractor */
00297   FloatCMP,             /* floating point comparator */
00298   FloatCVT,             /* floating point<->integer converter */
00299   FloatMULT,            /* floating point multiplier */
00300   FloatDIV,             /* floating point divider */
00301   FloatSQRT,            /* floating point square root */
00302   RdPort,               /* memory read port */
00303   WrPort,               /* memory write port */
00304   NUM_FU_CLASSES        /* total functional unit classes */
00305 };
00306 
00307 /* enum md_opcode -> enum md_fu_class, used by performance simulators */
00308 #define MD_OP_FUCLASS(OP)       (md_op2fu[OP])
00309 extern enum md_fu_class md_op2fu[];
00310 
00311 /* enum md_fu_class -> description string */
00312 #define MD_FU_NAME(FU)          (md_fu2name[FU])
00313 extern char *md_fu2name[];
00314 
00315 /* instruction flags */
00316 #define F_ICOMP         0x00000001      /* integer computation */
00317 #define F_FCOMP         0x00000002      /* FP computation */
00318 #define F_CTRL          0x00000004      /* control inst */
00319 #define F_UNCOND        0x00000008      /*   unconditional change */
00320 #define F_COND          0x00000010      /*   conditional change */
00321 #define F_MEM           0x00000020      /* memory access inst */
00322 #define F_LOAD          0x00000040      /*   load inst */
00323 #define F_STORE         0x00000080      /*   store inst */
00324 #define F_DISP          0x00000100      /*   displaced (R+C) addr mode */
00325 #define F_RR            0x00000200      /*   R+R addr mode */
00326 #define F_DIRECT        0x00000400      /*   direct addressing mode */
00327 #define F_TRAP          0x00000800      /* traping inst */
00328 #define F_LONGLAT       0x00001000      /* long latency inst (for sched) */
00329 #define F_DIRJMP        0x00002000      /* direct jump */
00330 #define F_INDIRJMP      0x00004000      /* indirect jump */
00331 #define F_CALL          0x00008000      /* function call */
00332 #define F_FPCOND        0x00010000      /* FP conditional branch */
00333 #define F_IMM           0x00020000      /* instruction has immediate operand */
00334 
00335 /* enum md_opcode -> opcode flags, used by simulators */
00336 #define MD_OP_FLAGS(OP)         (md_op2flags[OP])
00337 extern unsigned int md_op2flags[];
00338 
00339 
00340 /* integer register specifiers */
00341 #define RA              ((inst >> 21) & 0x1f)           /* reg source #1 */
00342 #define RB              ((inst >> 16) & 0x1f)           /* reg source #2 */
00343 #define RC              (inst & 0x1f)                   /* reg dest */
00344 
00345 /* returns 8-bit unsigned immediate field value */
00346 #define IMM             ((qword_t)((inst >> 13) & 0xff))
00347 
00348 /* returns 21-bit unsigned absolute jump target field value */
00349 #define TARG            (inst & 0x1fffff)
00350 
00351 /* load/store 16-bit unsigned offset field value */
00352 #define OFS             (inst & 0xffff)
00353 
00354 /* sign-extend operands */
00355 #define SEXT(X)                                                         \
00356   (((X) & 0x8000) ? ((sqword_t)(X) | LL(0xffffffffffff0000)) : (sqword_t)(X))
00357 
00358 #define SEXT21(X)                                                       \
00359   (((X) & 0x100000) ? ((sqword_t)(X) | LL(0xffffffffffe00000)) : (sqword_t)(X))
00360 
00361 #define SEXT32(X)                                                       \
00362   (((X) & 0x80000000) ? ((sqword_t)(X)|LL(0xffffffff00000000)) : (sqword_t)(X))
00363 
00364 /* test for arithmetic overflow */
00365 #define ARITH_OVFL(RESULT, OP1, OP2) ((RESULT) < (OP1) || (RESULT) < (OP2))
00366 
00367 /* test for NaN */
00368 #define IEEEFP_DBL_SIGN(Q)      ((Q) >> 63)
00369 #define IEEEFP_DBL_EXPONENT(Q)  (((Q) >> 52) & 0x7ff)
00370 #define IEEEFP_DBL_FRACTION(Q)  ((Q) & ULL(0xfffffffffffff))
00371 #define IS_IEEEFP_DBL_NAN(Q)                                            \
00372   ((IEEEFP_DBL_EXPONENT(Q) == 0x7ff) && (IEEEFP_DBL_FRACTION(Q)))
00373 
00374 /* default target PC handling */
00375 #ifndef SET_TPC
00376 #define SET_TPC(PC)     (void)0
00377 #endif /* SET_TPC */
00378 
00379 
00380 /*
00381  * various other helper macros/functions
00382  */
00383 
00384 /* non-zero if system call is an exit() */
00385 #define OSF_SYS_exit                    1
00386 #define MD_EXIT_SYSCALL(REGS)                                           \
00387   ((REGS)->regs_R[MD_REG_V0] == OSF_SYS_exit)
00388 
00389 /* non-zero if system call is a write to stdout/stderr */
00390 #define OSF_SYS_write                   4
00391 #define MD_OUTPUT_SYSCALL(REGS)                                         \
00392   ((REGS)->regs_R[MD_REG_V0] == OSF_SYS_write                           \
00393    && ((REGS)->regs_R[MD_REG_A0] == /* stdout */1                       \
00394        || (REGS)->regs_R[MD_REG_A0] == /* stderr */2))
00395 
00396 /* returns stream of an output system call, translated to host */
00397 #define MD_STREAM_FILENO(REGS)          ((REGS)->regs_R[MD_REG_A0])
00398 
00399 /* returns non-zero if instruction is a function call */
00400 #define MD_IS_CALL(OP)                  ((OP) == JSR || (OP) == BSR)
00401 
00402 /* returns non-zero if instruction is a function return */
00403 #define MD_IS_RETURN(OP)                ((OP) == RETN)
00404 
00405 /* returns non-zero if instruction is an indirect jump */
00406 #define MD_IS_INDIR(OP)                                                 \
00407   ((OP) == JMP || (OP) == JSR || (OP) == RETN || (OP) == JSR_COROUTINE)
00408 
00409 /* addressing mode probe, enums and strings */
00410 enum md_amode_type {
00411   md_amode_imm,         /* immediate addressing mode */
00412   md_amode_gp,          /* global data access through global pointer */
00413   md_amode_sp,          /* stack access through stack pointer */
00414   md_amode_fp,          /* stack access through frame pointer */
00415   md_amode_disp,        /* (reg + const) addressing */
00416   md_amode_rr,          /* (reg + reg) addressing */
00417   md_amode_NUM
00418 };
00419 extern char *md_amode_str[md_amode_NUM];
00420 
00421 /* addressing mode pre-probe FSM, must see all instructions */
00422 #define MD_AMODE_PREPROBE(OP, FSM)              { (FSM) = 0; }
00423 
00424 /* compute addressing mode, only for loads/stores */
00425 #define MD_AMODE_PROBE(AM, OP, FSM)                                     \
00426   {                                                                     \
00427     if (MD_OP_FLAGS(OP) & F_DISP)                                       \
00428       {                                                                 \
00429         if ((RB) == MD_REG_GP)                                          \
00430           (AM) = md_amode_gp;                                           \
00431         else if ((RB) == MD_REG_SP)                                     \
00432           (AM) = md_amode_sp;                                           \
00433         else if ((RB) == MD_REG_FP) /* && bind_to_seg(addr) == seg_stack */\
00434           (AM) = md_amode_fp;                                           \
00435         else                                                            \
00436           (AM) = md_amode_disp;                                         \
00437       }                                                                 \
00438     else if (MD_OP_FLAGS(OP) & F_RR)                                    \
00439       (AM) = md_amode_rr;                                               \
00440     else                                                                \
00441       panic("cannot decode addressing mode");                           \
00442   }
00443 
00444 /* addressing mode pre-probe FSM, after all loads and stores */
00445 #define MD_AMODE_POSTPROBE(FSM)                 /* nada... */
00446 
00447 
00448 /*
00449  * EIO package configuration/macros
00450  */
00451 
00452 /* expected EIO file format */
00453 #define MD_EIO_FILE_FORMAT              EIO_ALPHA_FORMAT
00454 
00455 #define MD_MISC_REGS_TO_EXO(REGS)                                       \
00456   exo_new(ec_list,                                                      \
00457           /*icnt*/exo_new(ec_integer, (exo_integer_t)sim_num_insn),     \
00458           /*PC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_PC),    \
00459           /*NPC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_NPC),  \
00460           /*FPCR*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.fpcr),\
00461           /*UNIQ*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.uniq),\
00462           NULL)
00463 
00464 #define MD_IREG_TO_EXO(REGS, IDX)                                       \
00465   exo_new(ec_address, (exo_integer_t)(REGS)->regs_R[IDX])
00466 
00467 #define MD_FREG_TO_EXO(REGS, IDX)                                       \
00468   exo_new(ec_address, (exo_integer_t)(REGS)->regs_F.q[IDX])
00469 
00470 #define MD_EXO_TO_MISC_REGS(EXO, ICNT, REGS)                            \
00471   /* check EXO format for errors... */                                  \
00472   if (!exo                                                              \
00473       || exo->ec != ec_list                                             \
00474       || !exo->as_list.head                                             \
00475       || exo->as_list.head->ec != ec_integer                            \
00476       || !exo->as_list.head->next                                       \
00477       || exo->as_list.head->next->ec != ec_address                      \
00478       || !exo->as_list.head->next->next                                 \
00479       || exo->as_list.head->next->next->ec != ec_address                \
00480       || !exo->as_list.head->next->next->next                           \
00481       || exo->as_list.head->next->next->next->ec != ec_integer          \
00482       || !exo->as_list.head->next->next->next->next                     \
00483       || exo->as_list.head->next->next->next->next->ec != ec_integer    \
00484       || exo->as_list.head->next->next->next->next->next != NULL)       \
00485     fatal("could not read EIO misc regs");                              \
00486   (ICNT) = (counter_t)exo->as_list.head->as_integer.val;                \
00487   (REGS)->regs_PC = (md_addr_t)exo->as_list.head->next->as_integer.val; \
00488   (REGS)->regs_NPC =                                                    \
00489     (md_addr_t)exo->as_list.head->next->next->as_integer.val;           \
00490   (REGS)->regs_C.fpcr =                                                 \
00491     (qword_t)exo->as_list.head->next->next->next->as_integer.val;       \
00492   (REGS)->regs_C.uniq =                                                 \
00493     (qword_t)exo->as_list.head->next->next->next->next->as_integer.val;
00494 
00495 #define MD_EXO_TO_IREG(EXO, REGS, IDX)                                  \
00496   ((REGS)->regs_R[IDX] = (qword_t)(EXO)->as_integer.val)
00497 
00498 #define MD_EXO_TO_FREG(EXO, REGS, IDX)                                  \
00499   ((REGS)->regs_F.q[IDX] = (qword_t)(EXO)->as_integer.val)
00500 
00501 #define MD_EXO_CMP_IREG(EXO, REGS, IDX)                                 \
00502   ((REGS)->regs_R[IDX] != (qword_t)(EXO)->as_integer.val)
00503 
00504 #define MD_FIRST_IN_REG                 0
00505 #define MD_LAST_IN_REG                  21
00506 
00507 #define MD_FIRST_OUT_REG                0
00508 #define MD_LAST_OUT_REG                 21
00509 
00510 
00511 /*
00512  * configure the EXO package
00513  */
00514 
00515 /* EXO pointer class */
00516 typedef qword_t exo_address_t;
00517 
00518 /* EXO integer class, 64-bit encoding */
00519 typedef qword_t exo_integer_t;
00520 
00521 /* EXO floating point class, 64-bit encoding */
00522 typedef double exo_float_t;
00523 
00524 
00525 /*
00526  * configure the stats package
00527  */
00528 
00529 /* counter stats */
00530 #define stat_reg_counter                stat_reg_sqword
00531 #define sc_counter                      sc_sqword
00532 #define for_counter                     for_sqword
00533 
00534 /* address stats */
00535 #define stat_reg_addr                   stat_reg_qword
00536 
00537 
00538 /*
00539  * configure the DLite! debugger
00540  */
00541 
00542 /* register bank specifier */
00543 enum md_reg_type {
00544   rt_gpr,               /* general purpose register */
00545   rt_lpr,               /* integer-precision floating pointer register */
00546   rt_fpr,               /* single-precision floating pointer register */
00547   rt_dpr,               /* double-precision floating pointer register */
00548   rt_ctrl,              /* control register */
00549   rt_PC,                /* program counter */
00550   rt_NPC,               /* next program counter */
00551   rt_NUM
00552 };
00553 
00554 /* register name specifier */
00555 struct md_reg_names_t {
00556   char *str;                    /* register name */
00557   enum md_reg_type file;        /* register file */
00558   int reg;                      /* register index */
00559 };
00560 
00561 /* symbolic register names, parser is case-insensitive */
00562 extern struct md_reg_names_t md_reg_names[];
00563 
00564 /* returns a register name string */
00565 char *md_reg_name(enum md_reg_type rt, int reg);
00566 
00567 /* default register accessor object */
00568 struct eval_value_t;
00569 struct regs_t;
00570 char *                                          /* err str, NULL for no err */
00571 md_reg_obj(struct regs_t *regs,                 /* registers to access */
00572            int is_write,                        /* access type */
00573            enum md_reg_type rt,                 /* reg bank to probe */
00574            int reg,                             /* register number */
00575            struct eval_value_t *val);           /* input, output */
00576 
00577 /* print integer REG(S) to STREAM */
00578 void md_print_ireg(md_gpr_t regs, int reg, FILE *stream);
00579 void md_print_iregs(md_gpr_t regs, FILE *stream);
00580 
00581 /* print floating point REG(S) to STREAM */
00582 void md_print_fpreg(md_fpr_t regs, int reg, FILE *stream);
00583 void md_print_fpregs(md_fpr_t regs, FILE *stream);
00584 
00585 /* print control REG(S) to STREAM */
00586 void md_print_creg(md_ctrl_t regs, int reg, FILE *stream);
00587 void md_print_cregs(md_ctrl_t regs, FILE *stream);
00588 
00589 /* xor checksum registers */
00590 word_t md_xor_regs(struct regs_t *regs);
00591 
00592 
00593 /*
00594  * configure sim-outorder specifics
00595  */
00596 
00597 /* primitive operation used to compute addresses within pipeline */
00598 #define MD_AGEN_OP              ADDQ
00599 
00600 /* NOP operation when injected into the pipeline */
00601 #define MD_NOP_OP               OP_NA
00602 
00603 /* non-zero for a valid address, used to determine if speculative accesses
00604    should access the DL1 data cache */
00605 #define MD_VALID_ADDR(ADDR)                                             \
00606   (((ADDR) >= ld_text_base && (ADDR) < (ld_text_base + ld_text_size))   \
00607    || ((ADDR) >= ld_data_base && (ADDR) < ld_brk_point)                 \
00608    || ((ADDR) >= (ld_stack_base - 16*1024*1024) && (ADDR) < ld_stack_base))
00609 
00610 /*
00611  * configure branch predictors
00612  */
00613 
00614 /* shift used to ignore branch address least significant bits, usually
00615    log2(sizeof(md_inst_t)) */
00616 #define MD_BR_SHIFT             2       /* log2(4) */
00617 
00618 
00619 /*
00620  * target-dependent routines
00621  */
00622 
00623 /* intialize the inst decoder, this function builds the ISA decode tables */
00624 void md_init_decoder(void);
00625 
00626 /* disassemble a SimpleScalar instruction */
00627 void
00628 md_print_insn(md_inst_t inst,           /* instruction to disassemble */
00629               md_addr_t pc,             /* addr of inst, used for PC-rels */
00630               FILE *stream);            /* output stream */
00631 
00632 #endif /* ALPHA_H */
00633 
00634 
00635 
00636 
00637 
00638 
00639 
00640 #if 0
00641 
00642 /* instruction/address formats */
00643 typedef qword_t MD_ADDR_TYPE;
00644 typedef qword_t MD_PTR_TYPE;
00645 typedef word_t MD_INST_TYPE;
00646 #define MD_INST_SIZE            sizeof(MD_INST_TYPE)
00647 
00648 /* virtual memory segment limits */
00649 #define MD_TEXT_BASE            0x20000000ULL
00650 #define MD_STACK_BASE           (MD_TEXT_BASE - (409600+4096))
00651 
00652 /* well known registers */
00653 enum { REG_V0, REG_A0=16, REG_A1, REG_A2, REG_A3, REG_A4, REG_A5, REG_ERR=7,
00654        REG_GP=29, REG_SP, REG_ZERO, REG_RA=26 };
00655 
00656 /* total number of register in processor 32I+32F+HI+LO+FCC+TMP+MEM+CTRL */
00657 #define MD_TOTAL_REGS                                                   \
00658   (MD_NUM_REGS+MD_NUM_REGS+/*FPCR*/1+/*UNIQ*/1+/*MEM*/1+/*CTRL*/1)
00659 
00660 /* inst check macros, activated if NO_ICHECKS is not defined (default) */
00661 #ifndef NO_ICHECKS
00662 
00663 /* instruction failure notification macro, this can be defined by the
00664    target simulator if, for example, the simulator wants to handle the
00665    instruction fault in a machine specific fashion; a string describing
00666    the instruction fault is passed to the IFAIL() macro */
00667 #ifndef IFAIL
00668 #define IFAIL(S)        fatal(S)
00669 #endif /* IFAIL */
00670 
00671 /* check for overflow in X+Y, both signed */
00672 #define OVER(X,Y)       (((((X) > 0) && ((Y) > 0)                       \
00673                            && (MAXINT_VAL - (X) < (Y)))                 \
00674                           ? IFAIL("+ overflow") : (void)0),             \
00675                          ((((X) < 0) && ((Y) < 0)                       \
00676                            && (-MAXINT_VAL - (X) > (Y)))                \
00677                           ? IFAIL("+ underflow") : (void)0))
00678 
00679 /* check for underflow in X-Y, both signed */
00680 #define UNDER(X,Y)      (((((X) > 0) && ((Y) < 0)                       \
00681                            && (MAXINT_VAL + (Y) < (X)))                 \
00682                           ? IFAIL("- overflow") : (void)0),             \
00683                          ((((X) < 0) && ((Y) > 0)                       \
00684                            && (-MAXINT_VAL + (Y) > (X)))                \
00685                           ? IFAIL("- underflow") : (void)0))
00686 
00687 /* check for divide by zero error, N is denom */
00688 #define DIV0(N)         (((N) == 0) ? IFAIL("divide by 0") : (void)0)
00689 
00690 /* check reg specifier N for required double integer word alignment */
00691 #define INTALIGN(N)     (((N) & 01)                                     \
00692                          ? IFAIL("bad INT register alignment") : (void)0)
00693 
00694 /* check reg specifier N for required double FP word alignment */
00695 #define FPALIGN(N)      (((N) & 01)                                     \
00696                          ? IFAIL("bad FP register alignment") : (void)0)
00697 
00698 /* check target address TARG for required jump target alignment */
00699 #define TALIGN(TARG)    (((TARG) & 0x7)                                 \
00700                          ? IFAIL("bad jump alignment") : (void)0)
00701 
00702 #else /* NO_ICHECKS */
00703 
00704 /* inst checks disables, change all checks to NOP expressions */
00705 #define OVER(X,Y)       ((void)0)
00706 #define UNDER(X,Y)      ((void)0)
00707 #define DIV0(N)         ((void)0)
00708 #define INTALIGN(N)     ((void)0)
00709 #define FPALIGN(N)      ((void)0)
00710 #define TALIGN(TARG)    ((void)0)
00711 
00712 #endif /* NO_ICHECKS */
00713 
00714 /* default division operator semantics, this operation is accessed through a
00715    macro because some simulators need to check for divide by zero faults
00716    before executing this operation */
00717 #define IDIV(A, B)      ((A) / (B))
00718 #define IMOD(A, B)      ((A) % (B))
00719 #define FDIV(A, B)      ((A) / (B))
00720 #define FINT(A)         ((int)A)
00721 
00722 #endif

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