"I am a person who works hard and plays hard."
Yuan Wei
Second Year Graduate Student Department of Computer Science
University of Virginia Charlottesville, VA 22903
Email: yw3f@cs.virginia.edu

Source Code Analysis

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sim-cache.c File Reference

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <assert.h>
#include "host.h"
#include "misc.h"
#include "machine.h"
#include "regs.h"
#include "memory.h"
#include "cache.h"
#include "loader.h"
#include "syscall.h"
#include "dlite.h"
#include "sim.h"
#include "machine.def"

Include dependency graph for sim-cache.c:

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Defines

Functions

Variables

Define Documentation

#define __READ_CACHE (  addr,
SRC_T    ) 
 

Value:

((dtlb                                                          \
    ? cache_access(dtlb, Read, (addr), NULL,                            \
                   sizeof(SRC_T), 0, NULL, NULL)                        \
    : 0),                                                               \
   (cache_dl1                                                           \
    ? cache_access(cache_dl1, Read, (addr), NULL,                       \
                   sizeof(SRC_T), 0, NULL, NULL)                        \
    : 0))

Definition at line 702 of file sim-cache.c.

#define __WRITE_CACHE (  addr,
DST_T    ) 
 

Value:

((dtlb                                                          \
    ? cache_access(dtlb, Write, (addr), NULL,                           \
                   sizeof(DST_T), 0, NULL, NULL)                        \
    : 0),                                                               \
   (cache_dl1                                                           \
    ? cache_access(cache_dl1, Write, (addr), NULL,                      \
                   sizeof(DST_T), 0, NULL, NULL)                        \
    : 0))

Definition at line 727 of file sim-cache.c.

#define CONNECT (  OP    ) 
 

#define CPC   (regs.regs_PC)
 

Definition at line 659 of file sim-cache.c.

#define DECLARE_FAULT (  FAULT    )     { fault = (FAULT); break; }
 

#define DEFINST (  OP,
MSK,
NAME,
OPFORM,
RES,
FLAGS,
O1,
O2,
I1,
I2,
I3    ) 
 

Value:

case OP:                                                        \
          SYMCAT(OP,_IMPL);                                             \
          break;

#define DEFLINK (  OP,
MSK,
NAME,
MASK,
SHIFT    ) 
 

Value:

case OP:                                                        \
          panic("attempted to execute a linking opcode");

#define FPCR   (regs.regs_C.fpcr)
 

Definition at line 692 of file sim-cache.c.

#define FPR (  N    )     (regs.regs_F.d[N])
 

Definition at line 688 of file sim-cache.c.

#define FPR_Q (  N    )     (regs.regs_F.q[N])
 

Definition at line 686 of file sim-cache.c.

#define GPR (  N    )     (regs.regs_R[N])
 

Definition at line 662 of file sim-cache.c.

#define IACOMPRESS (  A    )     (A)
 

Definition at line 302 of file sim-cache.c.

Referenced by sim_main().

#define ISCOMPRESS (  SZ    )     (SZ)
 

Definition at line 303 of file sim-cache.c.

Referenced by sim_main().

#define MAX_PCSTAT_VARS   8
 

Definition at line 160 of file sim-cache.c.

#define READ_BYTE (  SRC,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (SRC),                         \
   __READ_CACHE(addr, byte_t), MEM_READ_BYTE(mem, addr))

Definition at line 712 of file sim-cache.c.

#define READ_HALF (  SRC,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (SRC),                         \
   __READ_CACHE(addr, half_t), MEM_READ_HALF(mem, addr))

Definition at line 715 of file sim-cache.c.

#define READ_WORD (  SRC,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (SRC),                         \
   __READ_CACHE(addr, word_t), MEM_READ_WORD(mem, addr))

Definition at line 718 of file sim-cache.c.

#define SET_FPCR (  EXPR    )     (regs.regs_C.fpcr = (EXPR))
 

Definition at line 693 of file sim-cache.c.

#define SET_FPR (  N,
EXPR    )     (regs.regs_F.d[N] = (EXPR))
 

Definition at line 689 of file sim-cache.c.

#define SET_FPR_Q (  N,
EXPR    )     (regs.regs_F.q[N] = (EXPR))
 

Definition at line 687 of file sim-cache.c.

#define SET_GPR (  N,
EXPR    )     (regs.regs_R[N] = (EXPR))
 

Definition at line 663 of file sim-cache.c.

#define SET_NPC (  EXPR    )     (regs.regs_NPC = (EXPR))
 

Definition at line 656 of file sim-cache.c.

#define SET_UNIQ (  EXPR    )     (regs.regs_C.uniq = (EXPR))
 

Definition at line 695 of file sim-cache.c.

#define STATVAL (  STAT    ) 
 

Value:

((STAT)->sc == sc_int                                                   \
   ? (counter_t)*((STAT)->variant.for_int.var)                          \
   : ((STAT)->sc == sc_uint                                             \
      ? (counter_t)*((STAT)->variant.for_uint.var)                      \
      : ((STAT)->sc == sc_counter                                       \
         ? *((STAT)->variant.for_counter.var)                           \
         : (panic("bad stat class"), 0))))

Definition at line 166 of file sim-cache.c.

Referenced by ruu_dispatch(), sim_main(), and sim_reg_stats().

#define SYSCALL (  INST    ) 
 

Value:

(flush_on_syscalls                                                      \
   ? ((dtlb ? cache_flush(dtlb, 0) : 0),                                \
      (cache_dl1 ? cache_flush(cache_dl1, 0) : 0),                      \
      (cache_dl2 ? cache_flush(cache_dl2, 0) : 0),                      \
      sys_syscall(&regs, mem_access, mem, INST, TRUE))                  \
   : sys_syscall(&regs, dcache_access_fn, mem, INST, TRUE))

Definition at line 768 of file sim-cache.c.

#define UNIQ   (regs.regs_C.uniq)
 

Definition at line 694 of file sim-cache.c.

#define WRITE_BYTE (  SRC,
DST,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (DST),                         \
   __WRITE_CACHE(addr, byte_t), MEM_WRITE_BYTE(mem, addr, (SRC)))

Definition at line 737 of file sim-cache.c.

#define WRITE_HALF (  SRC,
DST,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (DST),                         \
   __WRITE_CACHE(addr, half_t), MEM_WRITE_HALF(mem, addr, (SRC)))

Definition at line 740 of file sim-cache.c.

#define WRITE_WORD (  SRC,
DST,
FAULT    ) 
 

Value:

((FAULT) = md_fault_none, addr = (DST),                         \
   __WRITE_CACHE(addr, word_t), MEM_WRITE_WORD(mem, addr, (SRC)))

Definition at line 743 of file sim-cache.c.

Function Documentation

char* cache_mstate_obj (  FILE *    stream,
char *    cmd,
struct regs_t *    regs,
struct mem_t *    mem
)  [static]
 

Definition at line 531 of file sim-cache.c.

References sim_print_stats().

Referenced by sim_load_prog(). 

00535 {
00536   /* just dump intermediate stats */
00537   sim_print_stats(stream);
00538 
00539   /* no error */
00540   return NULL;
00541 }

enum md_fault_type dcache_access_fn (  struct mem_t *    mem,
enum mem_cmd    cmd,
md_addr_t    addr,
void *    p,
int    nbytes
) 
 

Definition at line 754 of file sim-cache.c.

References cache_access(), mem_access(), and mem_cmd. 

00759 {
00760   if (dtlb)
00761     cache_access(dtlb, cmd, addr, NULL, nbytes, 0, NULL, NULL);
00762   if (cache_dl1)
00763     cache_access(cache_dl1, cmd, addr, NULL, nbytes, 0, NULL, NULL);
00764   return mem_access(mem, cmd, addr, p, nbytes);
00765 }

unsigned int dl1_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 177 of file sim-cache.c.

References cache_access(), mem_cmd, and tick_t.

Referenced by sim_check_options(). 

00182 {
00183   if (cache_dl2)
00184     {
00185       /* access next level of data cache hierarchy */
00186       return cache_access(cache_dl2, cmd, baddr, NULL, bsize,
00187                           /* now */now, /* pudata */NULL, /* repl addr */NULL);
00188     }
00189   else
00190     {
00191       /* access main memory, which is always done in the main simulator loop */
00192       return /* access latency, ignored */1;
00193     }
00194 }

unsigned int dl2_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 198 of file sim-cache.c.

References mem_cmd, and tick_t.

Referenced by sim_check_options(). 

00203 {
00204   /* this is a miss to the lowest level, so access main memory, which is
00205      always done in the main simulator loop */
00206   return /* access latency, ignored */1;
00207 }

unsigned int dtlb_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 264 of file sim-cache.c.

References mem_cmd, tick_t, and cache_blk_t::user_data.

Referenced by sim_check_options(). 

00269 {
00270   md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
00271 
00272   /* no real memory access, however, should have user data space attached */
00273   assert(phy_page_ptr);
00274 
00275   /* fake translation, for now... */
00276   *phy_page_ptr = 0;
00277 
00278   return /* access latency, ignored */1;
00279 }

unsigned int il1_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 211 of file sim-cache.c.

References cache_access(), mem_cmd, and tick_t.

Referenced by sim_check_options(). 

00216 {
00217   if (cache_il2)
00218     {
00219       /* access next level of inst cache hierarchy */
00220       return cache_access(cache_il2, cmd, baddr, NULL, bsize,
00221                           /* now */now, /* pudata */NULL, /* repl addr */NULL);
00222     }
00223   else
00224     {
00225       /* access main memory, which is always done in the main simulator loop */
00226       return /* access latency, ignored */1;
00227     }
00228 }

unsigned int il2_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 232 of file sim-cache.c.

References mem_cmd, and tick_t.

Referenced by sim_check_options(). 

00237 {
00238   /* this is a miss to the lowest level, so access main memory, which is
00239      always done in the main simulator loop */
00240   return /* access latency, ignored */1;
00241 }

unsigned int itlb_access_fn (  enum mem_cmd    cmd,
md_addr_t    baddr,
int    bsize,
struct cache_blk_t *    blk,
tick_t    now
)  [static]
 

Definition at line 245 of file sim-cache.c.

References mem_cmd, tick_t, and cache_blk_t::user_data.

Referenced by sim_check_options(). 

00250 {
00251   md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
00252 
00253   /* no real memory access, however, should have user data space attached */
00254   assert(phy_page_ptr);
00255 
00256   /* fake translation, for now... */
00257   *phy_page_ptr = 0;
00258 
00259   return /* access latency, ignored */1;
00260 }

void sim_aux_config (  FILE *    stream ) 
 

Definition at line 558 of file sim-cache.c. 

00559 {
00560   /* nada */
00561 }

void sim_aux_stats (  FILE *    stream ) 
 

Definition at line 635 of file sim-cache.c. 

00636 {
00637   /* nada */
00638 }

void sim_check_options (  struct opt_odb_t *    odb,
int    argc,
char **    argv
) 
 

Definition at line 384 of file sim-cache.c.

References cache_char2policy(), cache_create(), cache_dl1_opt, cache_dl2_opt, cache_il1_opt, cache_il2_opt, dl1_access_fn(), dl2_access_fn(), dtlb_access_fn(), dtlb_opt, FALSE, fatal(), il1_access_fn(), il2_access_fn(), itlb_access_fn(), itlb_opt, and mystricmp(). 

00386 {
00387   char name[128], c;
00388   int nsets, bsize, assoc;
00389 
00390   /* use a level 1 D-cache? */
00391   if (!mystricmp(cache_dl1_opt, "none"))
00392     {
00393       cache_dl1 = NULL;
00394 
00395       /* the level 2 D-cache cannot be defined */
00396       if (strcmp(cache_dl2_opt, "none"))
00397         fatal("the l1 data cache must defined if the l2 cache is defined");
00398       cache_dl2 = NULL;
00399     }
00400   else /* dl1 is defined */
00401     {
00402       if (sscanf(cache_dl1_opt, "%[^:]:%d:%d:%d:%c",
00403                  name, &nsets, &bsize, &assoc, &c) != 5)
00404         fatal("bad l1 D-cache parms: <name>:<nsets>:<bsize>:<assoc>:<repl>");
00405       cache_dl1 = cache_create(name, nsets, bsize, /* balloc */FALSE,
00406                                /* usize */0, assoc, cache_char2policy(c),
00407                                dl1_access_fn, /* hit latency */1);
00408 
00409       /* is the level 2 D-cache defined? */
00410       if (!mystricmp(cache_dl2_opt, "none"))
00411         cache_dl2 = NULL;
00412       else
00413         {
00414           if (sscanf(cache_dl2_opt, "%[^:]:%d:%d:%d:%c",
00415                      name, &nsets, &bsize, &assoc, &c) != 5)
00416             fatal("bad l2 D-cache parms: "
00417                   "<name>:<nsets>:<bsize>:<assoc>:<repl>");
00418           cache_dl2 = cache_create(name, nsets, bsize, /* balloc */FALSE,
00419                                    /* usize */0, assoc, cache_char2policy(c),
00420                                    dl2_access_fn, /* hit latency */1);
00421         }
00422     }
00423 
00424   /* use a level 1 I-cache? */
00425   if (!mystricmp(cache_il1_opt, "none"))
00426     {
00427       cache_il1 = NULL;
00428 
00429       /* the level 2 I-cache cannot be defined */
00430       if (strcmp(cache_il2_opt, "none"))
00431         fatal("the l1 inst cache must defined if the l2 cache is defined");
00432       cache_il2 = NULL;
00433     }
00434   else if (!mystricmp(cache_il1_opt, "dl1"))
00435     {
00436       if (!cache_dl1)
00437         fatal("I-cache l1 cannot access D-cache l1 as it's undefined");
00438       cache_il1 = cache_dl1;
00439 
00440       /* the level 2 I-cache cannot be defined */
00441       if (strcmp(cache_il2_opt, "none"))
00442         fatal("the l1 inst cache must defined if the l2 cache is defined");
00443       cache_il2 = NULL;
00444     }
00445   else if (!mystricmp(cache_il1_opt, "dl2"))
00446     {
00447       if (!cache_dl2)
00448         fatal("I-cache l1 cannot access D-cache l2 as it's undefined");
00449       cache_il1 = cache_dl2;
00450 
00451       /* the level 2 I-cache cannot be defined */
00452       if (strcmp(cache_il2_opt, "none"))
00453         fatal("the l1 inst cache must defined if the l2 cache is defined");
00454       cache_il2 = NULL;
00455     }
00456   else /* il1 is defined */
00457     {
00458       if (sscanf(cache_il1_opt, "%[^:]:%d:%d:%d:%c",
00459                  name, &nsets, &bsize, &assoc, &c) != 5)
00460         fatal("bad l1 I-cache parms: <name>:<nsets>:<bsize>:<assoc>:<repl>");
00461       cache_il1 = cache_create(name, nsets, bsize, /* balloc */FALSE,
00462                                /* usize */0, assoc, cache_char2policy(c),
00463                                il1_access_fn, /* hit latency */1);
00464 
00465       /* is the level 2 D-cache defined? */
00466       if (!mystricmp(cache_il2_opt, "none"))
00467         cache_il2 = NULL;
00468       else if (!mystricmp(cache_il2_opt, "dl2"))
00469         {
00470           if (!cache_dl2)
00471             fatal("I-cache l2 cannot access D-cache l2 as it's undefined");
00472           cache_il2 = cache_dl2;
00473         }
00474       else
00475         {
00476           if (sscanf(cache_il2_opt, "%[^:]:%d:%d:%d:%c",
00477                      name, &nsets, &bsize, &assoc, &c) != 5)
00478             fatal("bad l2 I-cache parms: "
00479                   "<name>:<nsets>:<bsize>:<assoc>:<repl>");
00480           cache_il2 = cache_create(name, nsets, bsize, /* balloc */FALSE,
00481                                    /* usize */0, assoc, cache_char2policy(c),
00482                                    il2_access_fn, /* hit latency */1);
00483         }
00484     }
00485 
00486   /* use an I-TLB? */
00487   if (!mystricmp(itlb_opt, "none"))
00488     itlb = NULL;
00489   else
00490     {
00491       if (sscanf(itlb_opt, "%[^:]:%d:%d:%d:%c",
00492                  name, &nsets, &bsize, &assoc, &c) != 5)
00493         fatal("bad TLB parms: <name>:<nsets>:<page_size>:<assoc>:<repl>");
00494       itlb = cache_create(name, nsets, bsize, /* balloc */FALSE,
00495                           /* usize */sizeof(md_addr_t), assoc,
00496                           cache_char2policy(c), itlb_access_fn,
00497                           /* hit latency */1);
00498     }
00499 
00500   /* use a D-TLB? */
00501   if (!mystricmp(dtlb_opt, "none"))
00502     dtlb = NULL;
00503   else
00504     {
00505       if (sscanf(dtlb_opt, "%[^:]:%d:%d:%d:%c",
00506                  name, &nsets, &bsize, &assoc, &c) != 5)
00507         fatal("bad TLB parms: <name>:<nsets>:<page_size>:<assoc>:<repl>");
00508       dtlb = cache_create(name, nsets, bsize, /* balloc */FALSE,
00509                           /* usize */sizeof(md_addr_t), assoc,
00510                           cache_char2policy(c), dtlb_access_fn,
00511                           /* hit latency */1);
00512     }
00513 }

void sim_init (  void    ) 
 

Definition at line 517 of file sim-cache.c.

References mem_create(), mem_init(), regs_init(), and sim_num_refs. 

00518 {
00519   sim_num_refs = 0;
00520 
00521   /* allocate and initialize register file */
00522   regs_init(&regs);
00523 
00524   /* allocate and initialize memory space */
00525   mem = mem_create("mem");
00526   mem_init(mem);
00527 }

void sim_load_prog (  char *    fname,
int    argc,
char **    argv,
char **    envp
) 
 

Definition at line 545 of file sim-cache.c.

References cache_mstate_obj(), dlite_init(), ld_load_prog(), and TRUE. 

00548 {
00549   /* load program text and data, set up environment, memory, and regs */
00550   ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);
00551 
00552   /* initialize the DLite debugger */
00553   dlite_init(md_reg_obj, dlite_mem_obj, cache_mstate_obj);
00554 }

void sim_main (  void    ) 
 

Definition at line 778 of file sim-cache.c.

References ACCESS_READ, ACCESS_WRITE, cache_access(), counter_t, md_fpr_t::d, dlite_check_break, dlite_main(), FALSE, fatal(), IACOMPRESS, ISCOMPRESS, max_insts, MD_FETCH_INST, MD_OP_FLAGS, MD_SET_OPCODE, panic(), pcstat_lastvals, pcstat_nelt, Read, regs_t::regs_F, regs_t::regs_NPC, regs_t::regs_PC, regs_t::regs_R, sim_num_refs, stat_add_samples(), STATVAL, and TRUE. 

00779 {
00780   int i;
00781   md_inst_t inst;
00782   register md_addr_t addr;
00783   enum md_opcode op;
00784   register int is_write;
00785   enum md_fault_type fault;
00786 
00787   fprintf(stderr, "sim: ** starting functional simulation w/ caches **\n");
00788 
00789   /* set up initial default next PC */
00790   regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
00791 
00792   /* check for DLite debugger entry condition */
00793   if (dlite_check_break(regs.regs_PC, /* no access */0, /* addr */0, 0, 0))
00794     dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
00795                sim_num_insn, &regs, mem);
00796 
00797   while (TRUE)
00798     {
00799       /* maintain $r0 semantics */
00800       regs.regs_R[MD_REG_ZERO] = 0;
00801 #ifdef TARGET_ALPHA
00802       regs.regs_F.d[MD_REG_ZERO] = 0.0;
00803 #endif /* TARGET_ALPHA */
00804 
00805       /* get the next instruction to execute */
00806       if (itlb)
00807         cache_access(itlb, Read, IACOMPRESS(regs.regs_PC),
00808                      NULL, ISCOMPRESS(sizeof(md_inst_t)), 0, NULL, NULL);
00809       if (cache_il1)
00810         cache_access(cache_il1, Read, IACOMPRESS(regs.regs_PC),
00811                      NULL, ISCOMPRESS(sizeof(md_inst_t)), 0, NULL, NULL);
00812       MD_FETCH_INST(inst, mem, regs.regs_PC);
00813 
00814       /* keep an instruction count */
00815       sim_num_insn++;
00816 
00817       /* set default reference address and access mode */
00818       addr = 0; is_write = FALSE;
00819 
00820       /* set default fault - none */
00821       fault = md_fault_none;
00822 
00823       /* decode the instruction */
00824       MD_SET_OPCODE(op, inst);
00825 
00826       /* execute the instruction */
00827       switch (op)
00828         {
00829 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00830         case OP:                                                        \
00831           SYMCAT(OP,_IMPL);                                             \
00832           break;
00833 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00834         case OP:                                                        \
00835           panic("attempted to execute a linking opcode");
00836 #define CONNECT(OP)
00837 #define DECLARE_FAULT(FAULT)                                            \
00838           { fault = (FAULT); break; }
00839 #include "machine.def"
00840         default:
00841           panic("attempted to execute a bogus opcode");
00842         }
00843 
00844       if (fault != md_fault_none)
00845         fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
00846 
00847       if (MD_OP_FLAGS(op) & F_MEM)
00848         {
00849           sim_num_refs++;
00850           if (MD_OP_FLAGS(op) & F_STORE)
00851             is_write = TRUE;
00852         }
00853 
00854       /* update any stats tracked by PC */
00855       for (i=0; i < pcstat_nelt; i++)
00856         {
00857           counter_t newval;
00858           int delta;
00859 
00860           /* check if any tracked stats changed */
00861           newval = STATVAL(pcstat_stats[i]);
00862           delta = newval - pcstat_lastvals[i];
00863           if (delta != 0)
00864             {
00865               stat_add_samples(pcstat_sdists[i], regs.regs_PC, delta);
00866               pcstat_lastvals[i] = newval;
00867             }
00868 
00869         }
00870 
00871       /* check for DLite debugger entry condition */
00872       if (dlite_check_break(regs.regs_NPC,
00873                             is_write ? ACCESS_WRITE : ACCESS_READ,
00874                             addr, sim_num_insn, sim_num_insn))
00875         dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, &regs, mem);
00876 
00877       /* go to the next instruction */
00878       regs.regs_PC = regs.regs_NPC;
00879       regs.regs_NPC += sizeof(md_inst_t);
00880 
00881       /* finish early? */
00882       if (max_insts && sim_num_insn >= max_insts)
00883         return;
00884     }
00885 }

void sim_reg_options (  struct opt_odb_t *    odb ) 
 

Definition at line 308 of file sim-cache.c.

References cache_dl1_opt, cache_dl2_opt, cache_il1_opt, cache_il2_opt, compress_icache_addrs, dtlb_opt, FALSE, flush_on_syscalls, itlb_opt, max_insts, opt_reg_flag(), opt_reg_header(), opt_reg_note(), opt_reg_string(), opt_reg_string_list(), opt_reg_uint(), pcstat_nelt, pcstat_vars, and TRUE. 

00309 {
00310   opt_reg_header(odb, 
00311 "sim-cache: This simulator implements a functional cache simulator.  Cache\n"
00312 "statistics are generated for a user-selected cache and TLB configuration,\n"
00313 "which may include up to two levels of instruction and data cache (with any\n"
00314 "levels unified), and one level of instruction and data TLBs.  No timing\n"
00315 "information is generated.\n"
00316                  );
00317 
00318   /* instruction limit */
00319   opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
00320                &max_insts, /* default */0,
00321                /* print */TRUE, /* format */NULL);
00322 
00323   opt_reg_string(odb, "-cache:dl1",
00324                  "l1 data cache config, i.e., {<config>|none}",
00325                  &cache_dl1_opt, "dl1:256:32:1:l", /* print */TRUE, NULL);
00326   opt_reg_note(odb,
00327 "  The cache config parameter <config> has the following format:\n"
00328 "\n"
00329 "    <name>:<nsets>:<bsize>:<assoc>:<repl>\n"
00330 "\n"
00331 "    <name>   - name of the cache being defined\n"
00332 "    <nsets>  - number of sets in the cache\n"
00333 "    <bsize>  - block size of the cache\n"
00334 "    <assoc>  - associativity of the cache\n"
00335 "    <repl>   - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random\n"
00336 "\n"
00337 "    Examples:   -cache:dl1 dl1:4096:32:1:l\n"
00338 "                -dtlb dtlb:128:4096:32:r\n"
00339                );
00340   opt_reg_string(odb, "-cache:dl2",
00341                  "l2 data cache config, i.e., {<config>|none}",
00342                  &cache_dl2_opt, "ul2:1024:64:4:l", /* print */TRUE, NULL);
00343   opt_reg_string(odb, "-cache:il1",
00344                  "l1 inst cache config, i.e., {<config>|dl1|dl2|none}",
00345                  &cache_il1_opt, "il1:256:32:1:l", /* print */TRUE, NULL);
00346   opt_reg_note(odb,
00347 "  Cache levels can be unified by pointing a level of the instruction cache\n"
00348 "  hierarchy at the data cache hiearchy using the \"dl1\" and \"dl2\" cache\n"
00349 "  configuration arguments.  Most sensible combinations are supported, e.g.,\n"
00350 "\n"
00351 "    A unified l2 cache (il2 is pointed at dl2):\n"
00352 "      -cache:il1 il1:128:64:1:l -cache:il2 dl2\n"
00353 "      -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l\n"
00354 "\n"
00355 "    Or, a fully unified cache hierarchy (il1 pointed at dl1):\n"
00356 "      -cache:il1 dl1\n"
00357 "      -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l\n"
00358                );
00359   opt_reg_string(odb, "-cache:il2",
00360                  "l2 instruction cache config, i.e., {<config>|dl2|none}",
00361                  &cache_il2_opt, "dl2", /* print */TRUE, NULL);
00362   opt_reg_string(odb, "-tlb:itlb",
00363                  "instruction TLB config, i.e., {<config>|none}",
00364                  &itlb_opt, "itlb:16:4096:4:l", /* print */TRUE, NULL);
00365   opt_reg_string(odb, "-tlb:dtlb",
00366                  "data TLB config, i.e., {<config>|none}",
00367                  &dtlb_opt, "dtlb:32:4096:4:l", /* print */TRUE, NULL);
00368   opt_reg_flag(odb, "-flush", "flush caches on system calls",
00369                &flush_on_syscalls, /* default */FALSE, /* print */TRUE, NULL);
00370   opt_reg_flag(odb, "-cache:icompress",
00371                "convert 64-bit inst addresses to 32-bit inst equivalents",
00372                &compress_icache_addrs, /* default */FALSE,
00373                /* print */TRUE, NULL);
00374 
00375   opt_reg_string_list(odb, "-pcstat",
00376                       "profile stat(s) against text addr's (mult uses ok)",
00377                       pcstat_vars, MAX_PCSTAT_VARS, &pcstat_nelt, NULL,
00378                       /* !print */FALSE, /* format */NULL, /* accrue */TRUE);
00379 
00380 }

void sim_reg_stats (  struct stat_sdb_t *    sdb ) 
 

Definition at line 565 of file sim-cache.c.

References cache_reg_stats(), stat_stat_t::desc, fatal(), ld_reg_stats(), mem_reg_stats(), stat_stat_t::name, pcstat_lastvals, pcstat_nelt, pcstat_vars, PF_COUNT, PF_PDF, stat_stat_t::sc, sc_int, sc_uint, sim_num_refs, stat_find_stat(), stat_reg_counter, stat_reg_formula(), stat_reg_int(), stat_reg_sdist(), and STATVAL. 

00566 {
00567   int i;
00568 
00569   /* register baseline stats */
00570   stat_reg_counter(sdb, "sim_num_insn",
00571                    "total number of instructions executed",
00572                    &sim_num_insn, sim_num_insn, NULL);
00573   stat_reg_counter(sdb, "sim_num_refs",
00574                    "total number of loads and stores executed",
00575                    &sim_num_refs, 0, NULL);
00576   stat_reg_int(sdb, "sim_elapsed_time",
00577                "total simulation time in seconds",
00578                &sim_elapsed_time, 0, NULL);
00579   stat_reg_formula(sdb, "sim_inst_rate",
00580                    "simulation speed (in insts/sec)",
00581                    "sim_num_insn / sim_elapsed_time", NULL);
00582 
00583   /* register cache stats */
00584   if (cache_il1
00585       && (cache_il1 != cache_dl1 && cache_il1 != cache_dl2))
00586     cache_reg_stats(cache_il1, sdb);
00587   if (cache_il2
00588       && (cache_il2 != cache_dl1 && cache_il2 != cache_dl2))
00589     cache_reg_stats(cache_il2, sdb);
00590   if (cache_dl1)
00591     cache_reg_stats(cache_dl1, sdb);
00592   if (cache_dl2)
00593     cache_reg_stats(cache_dl2, sdb);
00594   if (itlb)
00595     cache_reg_stats(itlb, sdb);
00596   if (dtlb)
00597     cache_reg_stats(dtlb, sdb);
00598 
00599   for (i=0; i<pcstat_nelt; i++)
00600     {
00601       char buf[512], buf1[512];
00602       struct stat_stat_t *stat;
00603 
00604       /* track the named statistical variable by text address */
00605 
00606       /* find it... */
00607       stat = stat_find_stat(sdb, pcstat_vars[i]);
00608       if (!stat)
00609         fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
00610 
00611       /* stat must be an integral type */
00612       if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
00613         fatal("`-pcstat' statistical variable `%s' is not an integral type",
00614               stat->name);
00615 
00616       /* register this stat */
00617       pcstat_stats[i] = stat;
00618       pcstat_lastvals[i] = STATVAL(stat);
00619 
00620       /* declare the sparce text distribution */
00621       sprintf(buf, "%s_by_pc", stat->name);
00622       sprintf(buf1, "%s (by text address)", stat->desc);
00623       pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
00624                                         /* initial value */0,
00625                                         /* print fmt */(PF_COUNT|PF_PDF),
00626                                         /* format */"0x%p %u %.2f",
00627                                         /* print fn */NULL);
00628     }
00629   ld_reg_stats(sdb);
00630   mem_reg_stats(mem, sdb);
00631 }

void sim_uninit (  void    ) 
 

Definition at line 642 of file sim-cache.c. 

00643 {
00644   /* nada */
00645 }

Variable Documentation

struct cache_t* cache_dl1 = NULL [static]
 

Definition at line 148 of file sim-cache.c.

char* cache_dl1_opt [static]
 

Definition at line 282 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

struct cache_t* cache_dl2 = NULL [static]
 

Definition at line 151 of file sim-cache.c.

char* cache_dl2_opt [static]
 

Definition at line 283 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

struct cache_t* cache_il1 = NULL [static]
 

Definition at line 142 of file sim-cache.c.

char* cache_il1_opt [static]
 

Definition at line 284 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

struct cache_t* cache_il2 = NULL [static]
 

Definition at line 145 of file sim-cache.c.

char* cache_il2_opt [static]
 

Definition at line 285 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

int compress_icache_addrs [static]
 

Definition at line 289 of file sim-cache.c.

Referenced by sim_reg_options().

struct cache_t* dtlb = NULL [static]
 

Definition at line 157 of file sim-cache.c.

char* dtlb_opt [static]
 

Definition at line 287 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

int flush_on_syscalls [static]
 

Definition at line 288 of file sim-cache.c.

Referenced by sim_reg_options().

struct cache_t* itlb = NULL [static]
 

Definition at line 154 of file sim-cache.c.

char* itlb_opt [static]
 

Definition at line 286 of file sim-cache.c.

Referenced by sim_check_options(), and sim_reg_options().

unsigned int max_insts [static]
 

Definition at line 139 of file sim-cache.c.

Referenced by sim_main(), and sim_reg_options().

struct mem_t* mem = NULL [static]
 

Definition at line 133 of file sim-cache.c.

counter_t pcstat_lastvals[MAX_PCSTAT_VARS] [static]
 

Definition at line 162 of file sim-cache.c.

Referenced by sim_main(), and sim_reg_stats().

int pcstat_nelt = 0 [static]
 

Definition at line 292 of file sim-cache.c.

Referenced by sim_main(), sim_reg_options(), and sim_reg_stats().

struct stat_stat_t* pcstat_sdists[MAX_PCSTAT_VARS] [static]
 

Definition at line 163 of file sim-cache.c.

struct stat_stat_t* pcstat_stats[MAX_PCSTAT_VARS] [static]
 

Definition at line 161 of file sim-cache.c.

char* pcstat_vars[MAX_PCSTAT_VARS] [static]
 

Definition at line 293 of file sim-cache.c.

Referenced by sim_reg_options(), and sim_reg_stats().

struct regs_t regs [static]
 

Definition at line 130 of file sim-cache.c.

counter_t sim_num_refs = 0 [static]
 

Definition at line 136 of file sim-cache.c.

Referenced by sim_init(), sim_main(), and sim_reg_stats().


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