"I am a person who works hard and plays hard."
Yuan Wei
Second Year Graduate Student Department of Computer Science
University of Virginia Charlottesville, VA 22903
Email: yw3f@cs.virginia.edu

Source Code Analysis

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sim-fast.c File Reference

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include "host.h"
#include "misc.h"
#include "machine.h"
#include "regs.h"
#include "memory.h"
#include "loader.h"
#include "syscall.h"
#include "dlite.h"
#include "sim.h"
#include "machine.def"

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Defines

Functions

Variables

Define Documentation

#define CONNECT (  OP    ) 
 

#define CPC   (regs.regs_PC)
 

Definition at line 280 of file sim-fast.c.

#define DECLARE_FAULT (  FAULT    )     { break; }
 

#define DEFINST (  OP,
MSK,
NAME,
OPFORM,
RES,
FLAGS,
O1,
O2,
I1,
I2,
I3    ) 
 

Value:

case OP:                                                        \
          SYMCAT(OP,_IMPL);                                             \
          break;

#define DEFLINK (  OP,
MSK,
NAME,
MASK,
SHIFT    ) 
 

Value:

case OP:                                                        \
          panic("attempted to execute a linking opcode");

#define FPCR   (regs.regs_C.fpcr)
 

Definition at line 313 of file sim-fast.c.

#define FPR (  N    )     (regs.regs_F.d[N])
 

Definition at line 309 of file sim-fast.c.

#define FPR_Q (  N    )     (regs.regs_F.q[N])
 

Definition at line 307 of file sim-fast.c.

#define GPR (  N    )     (regs.regs_R[N])
 

Definition at line 283 of file sim-fast.c.

 
#define INC_INSN_CTR (    )     sim_num_insn++
 

Definition at line 349 of file sim-fast.c.

#define READ_BYTE (  SRC,
FAULT    )     ((FAULT) = md_fault_none, MEM_READ_BYTE(mem, (SRC)))
 

Definition at line 323 of file sim-fast.c.

#define READ_HALF (  SRC,
FAULT    )     ((FAULT) = md_fault_none, MEM_READ_HALF(mem, (SRC)))
 

Definition at line 325 of file sim-fast.c.

#define READ_WORD (  SRC,
FAULT    )     ((FAULT) = md_fault_none, MEM_READ_WORD(mem, (SRC)))
 

Definition at line 327 of file sim-fast.c.

#define SET_FPCR (  EXPR    )     (regs.regs_C.fpcr = (EXPR))
 

Definition at line 314 of file sim-fast.c.

#define SET_FPR (  N,
EXPR    )     (regs.regs_F.d[N] = (EXPR))
 

Definition at line 310 of file sim-fast.c.

#define SET_FPR_Q (  N,
EXPR    )     (regs.regs_F.q[N] = (EXPR))
 

Definition at line 308 of file sim-fast.c.

#define SET_GPR (  N,
EXPR    )     (regs.regs_R[N] = (EXPR))
 

Definition at line 284 of file sim-fast.c.

#define SET_NPC (  EXPR    )     (regs.regs_NPC = (EXPR))
 

Definition at line 277 of file sim-fast.c.

#define SET_UNIQ (  EXPR    )     (regs.regs_C.uniq = (EXPR))
 

Definition at line 316 of file sim-fast.c.

#define SYSCALL (  INST    )     sys_syscall(&regs, mem_access, mem, INST, TRUE)
 

Definition at line 346 of file sim-fast.c.

#define UNIQ   (regs.regs_C.uniq)
 

Definition at line 315 of file sim-fast.c.

#define WRITE_BYTE (  SRC,
DST,
FAULT    )     ((FAULT) = md_fault_none, MEM_WRITE_BYTE(mem, (DST), (SRC)))
 

Definition at line 334 of file sim-fast.c.

#define WRITE_HALF (  SRC,
DST,
FAULT    )     ((FAULT) = md_fault_none, MEM_WRITE_HALF(mem, (DST), (SRC)))
 

Definition at line 336 of file sim-fast.c.

#define WRITE_WORD (  SRC,
DST,
FAULT    )     ((FAULT) = md_fault_none, MEM_WRITE_WORD(mem, (DST), (SRC)))
 

Definition at line 338 of file sim-fast.c.

 
#define ZERO_FP_REG (    )     regs.regs_F.d[MD_REG_ZERO] = 0.0
 

Definition at line 355 of file sim-fast.c.

Function Documentation

void sim_aux_config (  FILE *    stream ) 
 

Definition at line 253 of file sim-fast.c. 

00254 {
00255   /* nothing currently */
00256 }

void sim_aux_stats (  FILE *    stream ) 
 

Definition at line 260 of file sim-fast.c. 

00261 {
00262   /* nada */
00263 }

void sim_check_options (  struct opt_odb_t *    odb,
int    argc,
char **    argv
) 
 

Definition at line 166 of file sim-fast.c.

References fatal(). 

00167 {
00168   if (dlite_active)
00169     fatal("sim-fast does not support DLite debugging");
00170 }

void sim_init (  void    ) 
 

Definition at line 198 of file sim-fast.c.

References mem_create(), mem_init(), and regs_init(). 

00199 {
00200   /* allocate and initialize register file */
00201   regs_init(&regs);
00202 
00203   /* allocate and initialize memory space */
00204   mem = mem_create("mem");
00205   mem_init(mem);
00206 }

void sim_load_prog (  char *    fname,
int    argc,
char **    argv,
char **    envp
) 
 

Definition at line 210 of file sim-fast.c.

References ld_load_prog(), MD_FETCH_INST, MD_SET_OPCODE, mem_create(), MEM_WRITE_WORD, TRUE, and word_t. 

00213 {
00214   /* load program text and data, set up environment, memory, and regs */
00215   ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);
00216 
00217 #ifdef TARGET_ALPHA
00218   /* pre-decode text segment */
00219   {
00220     unsigned i, num_insn = (ld_text_size + 3) / 4;
00221 
00222     fprintf(stderr, "** pre-decoding %u insts...", num_insn);
00223 
00224     /* allocate decoded text space */
00225     dec = mem_create("dec");
00226 
00227     for (i=0; i < num_insn; i++)
00228       {
00229         enum md_opcode op;
00230         md_inst_t inst;
00231         md_addr_t PC;
00232 
00233         /* compute PC */
00234         PC = ld_text_base + i * sizeof(md_inst_t);
00235 
00236         /* get instruction from memory */
00237         MD_FETCH_INST(inst, mem, PC);
00238 
00239         /* decode the instruction */
00240         MD_SET_OPCODE(op, inst);
00241 
00242         /* insert into decoded opcode space */
00243         MEM_WRITE_WORD(dec, PC << 1, (word_t)op);
00244         MEM_WRITE_WORD(dec, (PC << 1)+sizeof(word_t), inst);
00245       }
00246     fprintf(stderr, "done\n");
00247   }
00248 #endif /* TARGET_ALPHA */
00249 }

void sim_main (  void    ) 
 

Definition at line 362 of file sim-fast.c.

References __UNCHK_MEM_READ, md_fpr_t::d, fatal(), MD_FETCH_INST, MD_SET_OPCODE, panic(), regs_t::regs_F, regs_t::regs_NPC, regs_t::regs_PC, regs_t::regs_R, and word_t. 

00363 {
00364 #ifdef USE_JUMP_TABLE
00365   /* the jump table employs GNU GCC label extensions to construct an array
00366      of pointers to instruction implementation code, the simulator then uses
00367      the table to lookup the location of instruction's implementing code, a
00368      GNU GCC `goto' extension is then used to jump to the inst's implementing
00369      code through the op_jump table; as a result, there is no need for
00370      a main simulator loop, which eliminates one branch from the simulator
00371      interpreter - crazy, no!?!? */
00372 
00373   /* instruction jump table, this code is GNU GCC specific */
00374   static void *op_jump[/* max opcodes */] = {
00375     &&opcode_NA, /* NA */
00376 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00377     &&opcode_##OP,
00378 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00379     &&opcode_##OP,
00380 #define CONNECT(OP)
00381 #include "machine.def"
00382   };
00383 #endif /* USE_JUMP_TABLE */
00384 
00385   /* register allocate instruction buffer */
00386   register md_inst_t inst;
00387 
00388   /* decoded opcode */
00389   register enum md_opcode op;
00390 
00391   fprintf(stderr, "sim: ** starting *fast* functional simulation **\n");
00392 
00393   /* must have natural byte/word ordering */
00394   if (sim_swap_bytes || sim_swap_words)
00395     fatal("sim: *fast* functional simulation cannot swap bytes or words");
00396 
00397 #ifdef USE_JUMP_TABLE
00398 
00399   regs.regs_NPC = regs.regs_PC;
00400 
00401   /* load instruction */
00402   MD_FETCH_INST(inst, mem, regs.regs_NPC);
00403 
00404   /* jump to instruction implementation */
00405   MD_SET_OPCODE(op, inst);
00406   goto *op_jump[op];
00407 
00408 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00409   opcode_##OP:                                                          \
00410     /* maintain $r0 semantics */                                        \
00411     regs.regs_R[MD_REG_ZERO] = 0;                                       \
00412     ZERO_FP_REG();                                                      \
00413                                                                         \
00414     /* keep an instruction count */                                     \
00415     INC_INSN_CTR();                                                     \
00416                                                                         \
00417     /* locate next instruction */                                       \
00418     regs.regs_PC = regs.regs_NPC;                                       \
00419                                                                         \
00420     /* set up default next PC */                                        \
00421     regs.regs_NPC += sizeof(md_inst_t);                                 \
00422                                                                         \
00423     /* execute the instruction */                                       \
00424     SYMCAT(OP,_IMPL);                                                   \
00425                                                                         \
00426     /* get the next instruction */                                      \
00427     MD_FETCH_INST(inst, mem, regs.regs_NPC);                            \
00428                                                                         \
00429     /* jump to instruction implementation */                            \
00430     MD_SET_OPCODE(op, inst);                                            \
00431     goto *op_jump[op];
00432 
00433 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00434   opcode_##OP:                                                          \
00435     panic("attempted to execute a linking opcode");
00436 #define CONNECT(OP)
00437 #define DECLARE_FAULT(FAULT)                                            \
00438           { /* uncaught... */break; }
00439 #include "machine.def"
00440 
00441   opcode_NA:
00442     panic("attempted to execute a bogus opcode");
00443 
00444   /* should not get here... */
00445   panic("exited sim-fast main loop");
00446 
00447 #else /* !USE_JUMP_TABLE */
00448 
00449   /* set up initial default next PC */
00450   regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
00451 
00452   while (TRUE)
00453     {
00454       /* maintain $r0 semantics */
00455       regs.regs_R[MD_REG_ZERO] = 0;
00456 #ifdef TARGET_ALPHA
00457       regs.regs_F.d[MD_REG_ZERO] = 0.0;
00458 #endif /* TARGET_ALPHA */
00459 
00460       /* keep an instruction count */
00461 #ifndef NO_INSN_COUNT
00462       sim_num_insn++;
00463 #endif /* !NO_INSN_COUNT */
00464 
00465 #ifdef TARGET_ALPHA
00466       /* load predecoded instruction */
00467       op = (enum md_opcode)__UNCHK_MEM_READ(dec, regs.regs_PC << 1, word_t);
00468       inst =
00469         __UNCHK_MEM_READ(dec, (regs.regs_PC << 1)+sizeof(word_t), md_inst_t);
00470 #else /* !TARGET_ALPHA */
00471       /* load instruction */
00472       MD_FETCH_INST(inst, mem, regs.regs_PC);
00473 
00474       /* decode the instruction */
00475       MD_SET_OPCODE(op, inst);
00476 #endif
00477 
00478       /* execute the instruction */
00479       switch (op)
00480         {
00481 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00482         case OP:                                                        \
00483           SYMCAT(OP,_IMPL);                                             \
00484           break;
00485 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00486         case OP:                                                        \
00487           panic("attempted to execute a linking opcode");
00488 #define CONNECT(OP)
00489 #define DECLARE_FAULT(FAULT)                                            \
00490           { /* uncaught... */break; }
00491 #include "machine.def"
00492         default:
00493           panic("attempted to execute a bogus opcode");
00494         }
00495 
00496       /* execute next instruction */
00497       regs.regs_PC = regs.regs_NPC;
00498       regs.regs_NPC += sizeof(md_inst_t);
00499     }
00500 
00501 #endif /* USE_JUMP_TABLE */
00502 }

void sim_reg_options (  struct opt_odb_t *    odb ) 
 

Definition at line 151 of file sim-fast.c.

References opt_reg_header(). 

00152 {
00153   opt_reg_header(odb, 
00154 "sim-fast: This simulator implements a very fast functional simulator.  This\n"
00155 "functional simulator implementation is much more difficult to digest than\n"
00156 "the simpler, cleaner sim-safe functional simulator.  By default, this\n"
00157 "simulator performs no instruction error checking, as a result, any\n"
00158 "instruction errors will manifest as simulator execution errors, possibly\n"
00159 "causing sim-fast to execute incorrectly or dump core.  Such is the\n"
00160 "price we pay for speed!!!!\n"
00161                  );
00162 }

void sim_reg_stats (  struct stat_sdb_t *    sdb ) 
 

Definition at line 174 of file sim-fast.c.

References ld_reg_stats(), mem_reg_stats(), stat_reg_counter, stat_reg_formula(), and stat_reg_int(). 

00175 {
00176 #ifndef NO_INSN_COUNT
00177   stat_reg_counter(sdb, "sim_num_insn",
00178                    "total number of instructions executed",
00179                    &sim_num_insn, sim_num_insn, NULL);
00180 #endif /* !NO_INSN_COUNT */
00181   stat_reg_int(sdb, "sim_elapsed_time",
00182                "total simulation time in seconds",
00183                &sim_elapsed_time, 0, NULL);
00184 #ifndef NO_INSN_COUNT
00185   stat_reg_formula(sdb, "sim_inst_rate",
00186                    "simulation speed (in insts/sec)",
00187                    "sim_num_insn / sim_elapsed_time", NULL);
00188 #endif /* !NO_INSN_COUNT */
00189   ld_reg_stats(sdb);
00190   mem_reg_stats(mem, sdb);
00191 #ifdef TARGET_ALPHA
00192   mem_reg_stats(dec, sdb);
00193 #endif
00194 }

void sim_uninit (  void    ) 
 

Definition at line 267 of file sim-fast.c. 

00268 {
00269   /* nada */
00270 }

Variable Documentation

struct mem_t* dec = NULL [static]
 

Definition at line 146 of file sim-fast.c.

struct mem_t* mem = NULL [static]
 

Definition at line 142 of file sim-fast.c.

struct regs_t regs [static]
 

Definition at line 139 of file sim-fast.c.


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