Document Title

case OP:                                                        \
          SYMCAT(OP,_IMPL);                                             \
          break;

case OP:                                                        \
          panic("attempted to execute a linking opcode");

00211 {
00212   /* nothing currently */
00213 }

00218 {
00219   /* nada */
00220 }

00157 {
00158   /* nada */
00159 }

00184 {
00185   sim_num_refs = 0;
00186 
00187   /* allocate and initialize register file */
00188   regs_init(&regs);
00189 
00190   /* allocate and initialize memory space */
00191   mem = mem_create("mem");
00192   mem_init(mem);
00193 }

00200 {
00201   /* load program text and data, set up environment, memory, and regs */
00202   ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);
00203 
00204   /* initialize the DLite debugger */
00205   dlite_init(md_reg_obj, dlite_mem_obj, dlite_mstate_obj);
00206 }

00313 {
00314   md_inst_t inst;
00315   register md_addr_t addr;
00316   enum md_opcode op;
00317   register int is_write;
00318   enum md_fault_type fault;
00319 
00320   fprintf(stderr, "sim: ** starting functional simulation **\n");
00321 
00322   /* set up initial default next PC */
00323   regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
00324 
00325   /* check for DLite debugger entry condition */
00326   if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
00327     dlite_main(regs.regs_PC - sizeof(md_inst_t),
00328                regs.regs_PC, sim_num_insn, &regs, mem);
00329 
00330   while (TRUE)
00331     {
00332       /* maintain $r0 semantics */
00333       regs.regs_R[MD_REG_ZERO] = 0;
00334 #ifdef TARGET_ALPHA
00335       regs.regs_F.d[MD_REG_ZERO] = 0.0;
00336 #endif /* TARGET_ALPHA */
00337 
00338       /* get the next instruction to execute */
00339       MD_FETCH_INST(inst, mem, regs.regs_PC);
00340 
00341       /* keep an instruction count */
00342       sim_num_insn++;
00343 
00344       /* set default reference address and access mode */
00345       addr = 0; is_write = FALSE;
00346 
00347       /* set default fault - none */
00348       fault = md_fault_none;
00349 
00350       /* decode the instruction */
00351       MD_SET_OPCODE(op, inst);
00352 
00353       /* execute the instruction */
00354       switch (op)
00355         {
00356 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00357         case OP:                                                        \
00358           SYMCAT(OP,_IMPL);                                             \
00359           break;
00360 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00361         case OP:                                                        \
00362           panic("attempted to execute a linking opcode");
00363 #define CONNECT(OP)
00364 #define DECLARE_FAULT(FAULT)                                            \
00365           { fault = (FAULT); break; }
00366 #include "machine.def"
00367         default:
00368           panic("attempted to execute a bogus opcode");
00369       }
00370 
00371       if (fault != md_fault_none)
00372         fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
00373 
00374       if (verbose)
00375         {
00376           myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
00377                     sim_num_insn, md_xor_regs(&regs), regs.regs_PC);
00378           md_print_insn(inst, regs.regs_PC, stderr);
00379           if (MD_OP_FLAGS(op) & F_MEM)
00380             myfprintf(stderr, "  mem: 0x%08p", addr);
00381           fprintf(stderr, "\n");
00382           /* fflush(stderr); */
00383         }
00384 
00385       if (MD_OP_FLAGS(op) & F_MEM)
00386         {
00387           sim_num_refs++;
00388           if (MD_OP_FLAGS(op) & F_STORE)
00389             is_write = TRUE;
00390         }
00391 
00392       /* check for DLite debugger entry condition */
00393       if (dlite_check_break(regs.regs_NPC,
00394                             is_write ? ACCESS_WRITE : ACCESS_READ,
00395                             addr, sim_num_insn, sim_num_insn))
00396         dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, &regs, mem);
00397 
00398       /* go to the next instruction */
00399       regs.regs_PC = regs.regs_NPC;
00400       regs.regs_NPC += sizeof(md_inst_t);
00401 
00402       /* finish early? */
00403       if (max_insts && sim_num_insn >= max_insts)
00404         return;
00405     }
00406 }

00138 {
00139   opt_reg_header(odb, 
00140 "sim-safe: This simulator implements a functional simulator.  This\n"
00141 "functional simulator is the simplest, most user-friendly simulator in the\n"
00142 "simplescalar tool set.  Unlike sim-fast, this functional simulator checks\n"
00143 "for all instruction errors, and the implementation is crafted for clarity\n"
00144 "rather than speed.\n"
00145                  );
00146 
00147   /* instruction limit */
00148   opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
00149                &max_insts, /* default */0,
00150                /* print */TRUE, /* format */NULL);
00151 
00152 }

00164 {
00165   stat_reg_counter(sdb, "sim_num_insn",
00166                    "total number of instructions executed",
00167                    &sim_num_insn, sim_num_insn, NULL);
00168   stat_reg_counter(sdb, "sim_num_refs",
00169                    "total number of loads and stores executed",
00170                    &sim_num_refs, 0, NULL);
00171   stat_reg_int(sdb, "sim_elapsed_time",
00172                "total simulation time in seconds",
00173                &sim_elapsed_time, 0, NULL);
00174   stat_reg_formula(sdb, "sim_inst_rate",
00175                    "simulation speed (in insts/sec)",
00176                    "sim_num_insn / sim_elapsed_time", NULL);
00177   ld_reg_stats(sdb);
00178   mem_reg_stats(mem, sdb);
00179 }

00225 {
00226   /* nada */
00227 }

sim-safe.c File Reference

Defines

Functions

Variables

Define Documentation

Function Documentation

Variable Documentation


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