Document Title

00355 {
00356   /* nothing currently */
00357 }

00362 {
00363   /* nada */
00364 }

00206 {
00207   if (!mystricmp(pred_type, "taken"))
00208     {
00209       /* static predictor, not taken */
00210       pred = bpred_create(BPredTaken, 0, 0, 0, 0, 0, 0, 0, 0, 0);
00211     }
00212   else if (!mystricmp(pred_type, "nottaken"))
00213     {
00214       /* static predictor, taken */
00215       pred = bpred_create(BPredNotTaken, 0, 0, 0, 0, 0, 0, 0, 0, 0);
00216     }
00217   else if (!mystricmp(pred_type, "bimod"))
00218     {
00219       if (bimod_nelt != 1)
00220         fatal("bad bimod predictor config (<table_size>)");
00221       if (btb_nelt != 2)
00222         fatal("bad btb config (<num_sets> <associativity>)");
00223 
00224       /* bimodal predictor, bpred_create() checks BTB_SIZE */
00225       pred = bpred_create(BPred2bit,
00226                           /* bimod table size */bimod_config[0],
00227                           /* 2lev l1 size */0,
00228                           /* 2lev l2 size */0,
00229                           /* meta table size */0,
00230                           /* history reg size */0,
00231                           /* history xor address */0,
00232                           /* btb sets */btb_config[0],
00233                           /* btb assoc */btb_config[1],
00234                           /* ret-addr stack size */ras_size);
00235     }
00236   else if (!mystricmp(pred_type, "2lev"))
00237     {
00238       /* 2-level adaptive predictor, bpred_create() checks args */
00239       if (twolev_nelt != 4)
00240         fatal("bad 2-level pred config (<l1size> <l2size> <hist_size> <xor>)");
00241       if (btb_nelt != 2)
00242         fatal("bad btb config (<num_sets> <associativity>)");
00243 
00244       pred = bpred_create(BPred2Level,
00245                           /* bimod table size */0,
00246                           /* 2lev l1 size */twolev_config[0],
00247                           /* 2lev l2 size */twolev_config[1],
00248                           /* meta table size */0,
00249                           /* history reg size */twolev_config[2],
00250                           /* history xor address */twolev_config[3],
00251                           /* btb sets */btb_config[0],
00252                           /* btb assoc */btb_config[1],
00253                           /* ret-addr stack size */ras_size);
00254     }
00255   else if (!mystricmp(pred_type, "comb"))
00256     {
00257       /* combining predictor, bpred_create() checks args */
00258       if (twolev_nelt != 4)
00259         fatal("bad 2-level pred config (<l1size> <l2size> <hist_size> <xor>)");
00260       if (bimod_nelt != 1)
00261         fatal("bad bimod predictor config (<table_size>)");
00262       if (comb_nelt != 1)
00263         fatal("bad combining predictor config (<meta_table_size>)");
00264       if (btb_nelt != 2)
00265         fatal("bad btb config (<num_sets> <associativity>)");
00266 
00267       pred = bpred_create(BPredComb,
00268                           /* bimod table size */bimod_config[0],
00269                           /* l1 size */twolev_config[0],
00270                           /* l2 size */twolev_config[1],
00271                           /* meta table size */comb_config[0],
00272                           /* history reg size */twolev_config[2],
00273                           /* history xor address */twolev_config[3],
00274                           /* btb sets */btb_config[0],
00275                           /* btb assoc */btb_config[1],
00276                           /* ret-addr stack size */ras_size);
00277     }
00278   else
00279     fatal("cannot parse predictor type `%s'", pred_type);
00280 }

00314 {
00315   sim_num_refs = 0;
00316 
00317   /* allocate and initialize register file */
00318   regs_init(&regs);
00319 
00320   /* allocate and initialize memory space */
00321   mem = mem_create("mem");
00322   mem_init(mem);
00323 }

00344 {
00345   /* load program text and data, set up environment, memory, and regs */
00346   ld_load_prog(fname, argc, argv, envp, &regs, mem, TRUE);
00347 
00348   /* initialize the DLite debugger */
00349   dlite_init(md_reg_obj, dlite_mem_obj, bpred_mstate_obj);
00350 }

00461 {
00462   md_inst_t inst;
00463   register md_addr_t addr, target_PC;
00464   enum md_opcode op;
00465   register int is_write;
00466   int stack_idx;
00467   enum md_fault_type fault;
00468 
00469   fprintf(stderr, "sim: ** starting functional simulation w/ predictors **\n");
00470 
00471   /* set up initial default next PC */
00472   regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
00473 
00474   /* check for DLite debugger entry condition */
00475   if (dlite_check_break(regs.regs_PC, /* no access */0, /* addr */0, 0, 0))
00476     dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
00477                sim_num_insn, &regs, mem);
00478 
00479   while (TRUE)
00480     {
00481       /* maintain $r0 semantics */
00482       regs.regs_R[MD_REG_ZERO] = 0;
00483 #ifdef TARGET_ALPHA
00484       regs.regs_F.d[MD_REG_ZERO] = 0.0;
00485 #endif /* TARGET_ALPHA */
00486 
00487       /* get the next instruction to execute */
00488       MD_FETCH_INST(inst, mem, regs.regs_PC);
00489 
00490       /* keep an instruction count */
00491       sim_num_insn++;
00492 
00493       /* set default reference address and access mode */
00494       addr = 0; is_write = FALSE;
00495 
00496       /* set default fault - none */
00497       fault = md_fault_none;
00498 
00499       /* decode the instruction */
00500       MD_SET_OPCODE(op, inst);
00501 
00502       /* execute the instruction */
00503       switch (op)
00504         {
00505 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3)            \
00506         case OP:                                                        \
00507           SYMCAT(OP,_IMPL);                                             \
00508           break;
00509 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT)                                 \
00510         case OP:                                                        \
00511           panic("attempted to execute a linking opcode");
00512 #define CONNECT(OP)
00513 #define DECLARE_FAULT(FAULT)                                            \
00514           { fault = (FAULT); break; }
00515 #include "machine.def"
00516         default:
00517           panic("attempted to execute a bogus opcode");
00518       }
00519 
00520       if (fault != md_fault_none)
00521         fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
00522 
00523       if (MD_OP_FLAGS(op) & F_MEM)
00524         {
00525           sim_num_refs++;
00526           if (MD_OP_FLAGS(op) & F_STORE)
00527             is_write = TRUE;
00528         }
00529 
00530       if (MD_OP_FLAGS(op) & F_CTRL)
00531         {
00532           md_addr_t pred_PC;
00533           struct bpred_update_t update_rec;
00534 
00535           sim_num_branches++;
00536 
00537           if (pred)
00538             {
00539               /* get the next predicted fetch address */
00540               pred_PC = bpred_lookup(pred,
00541                                      /* branch addr */regs.regs_PC,
00542                                      /* target */target_PC,
00543                                      /* inst opcode */op,
00544                                      /* call? */MD_IS_CALL(op),
00545                                      /* return? */MD_IS_RETURN(op),
00546                                      /* stash an update ptr */&update_rec,
00547                                      /* stash return stack ptr */&stack_idx);
00548 
00549               /* valid address returned from branch predictor? */
00550               if (!pred_PC)
00551                 {
00552                   /* no predicted taken target, attempt not taken target */
00553                   pred_PC = regs.regs_PC + sizeof(md_inst_t);
00554                 }
00555 
00556               bpred_update(pred,
00557                            /* branch addr */regs.regs_PC,
00558                            /* resolved branch target */regs.regs_NPC,
00559                            /* taken? */regs.regs_NPC != (regs.regs_PC +
00560                                                          sizeof(md_inst_t)),
00561                            /* pred taken? */pred_PC != (regs.regs_PC +
00562                                                         sizeof(md_inst_t)),
00563                            /* correct pred? */pred_PC == regs.regs_NPC,
00564                            /* opcode */op,
00565                            /* predictor update pointer */&update_rec);
00566             }
00567         }
00568 
00569       /* check for DLite debugger entry condition */
00570       if (dlite_check_break(regs.regs_NPC,
00571                             is_write ? ACCESS_WRITE : ACCESS_READ,
00572                             addr, sim_num_insn, sim_num_insn))
00573         dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, &regs, mem);
00574 
00575       /* go to the next instruction */
00576       regs.regs_PC = regs.regs_NPC;
00577       regs.regs_NPC += sizeof(md_inst_t);
00578 
00579       /* finish early? */
00580       if (max_insts && sim_num_insn >= max_insts)
00581         return;
00582     }
00583 }

00233 {
00234 #if 0 /* not portable... :-( */
00235   extern char etext, *sbrk(int);
00236 #endif
00237 
00238   if (!running)
00239     return;
00240 
00241   /* get stats time */
00242   sim_end_time = time((time_t *)NULL);
00243   sim_elapsed_time = MAX(sim_end_time - sim_start_time, 1);
00244 
00245 #if 0 /* not portable... :-( */
00246   /* compute simulator memory usage */
00247   sim_mem_usage = (sbrk(0) - &etext) / 1024;
00248 #endif
00249 
00250   /* print simulation stats */
00251   fprintf(fd, "\nsim: ** simulation statistics **\n");
00252   stat_print_stats(sim_sdb, fd);
00253   sim_aux_stats(fd);
00254   fprintf(fd, "\n");
00255 }

00140 {
00141   opt_reg_header(odb, 
00142 "sim-bpred: This simulator implements a branch predictor analyzer.\n"
00143                  );
00144 
00145   /* branch predictor options */
00146   opt_reg_note(odb,
00147 "  Branch predictor configuration examples for 2-level predictor:\n"
00148 "    Configurations:   N, M, W, X\n"
00149 "      N   # entries in first level (# of shift register(s))\n"
00150 "      W   width of shift register(s)\n"
00151 "      M   # entries in 2nd level (# of counters, or other FSM)\n"
00152 "      X   (yes-1/no-0) xor history and address for 2nd level index\n"
00153 "    Sample predictors:\n"
00154 "      GAg     : 1, W, 2^W, 0\n"
00155 "      GAp     : 1, W, M (M > 2^W), 0\n"
00156 "      PAg     : N, W, 2^W, 0\n"
00157 "      PAp     : N, W, M (M == 2^(N+W)), 0\n"
00158 "      gshare  : 1, W, 2^W, 1\n"
00159 "  Predictor `comb' combines a bimodal and a 2-level predictor.\n"
00160                );
00161 
00162   /* instruction limit */
00163   opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
00164                &max_insts, /* default */0,
00165                /* print */TRUE, /* format */NULL);
00166 
00167   opt_reg_string(odb, "-bpred",
00168                  "branch predictor type {nottaken|taken|bimod|2lev|comb}",
00169                  &pred_type, /* default */"bimod",
00170                  /* print */TRUE, /* format */NULL);
00171 
00172   opt_reg_int_list(odb, "-bpred:bimod",
00173                    "bimodal predictor config (<table size>)",
00174                    bimod_config, bimod_nelt, &bimod_nelt,
00175                    /* default */bimod_config,
00176                    /* print */TRUE, /* format */NULL, /* !accrue */FALSE);
00177 
00178   opt_reg_int_list(odb, "-bpred:2lev",
00179                    "2-level predictor config "
00180                    "(<l1size> <l2size> <hist_size> <xor>)",
00181                    twolev_config, twolev_nelt, &twolev_nelt,
00182                    /* default */twolev_config,
00183                    /* print */TRUE, /* format */NULL, /* !accrue */FALSE);
00184 
00185   opt_reg_int_list(odb, "-bpred:comb",
00186                    "combining predictor config (<meta_table_size>)",
00187                    comb_config, comb_nelt, &comb_nelt,
00188                    /* default */comb_config,
00189                    /* print */TRUE, /* format */NULL, /* !accrue */FALSE);
00190 
00191   opt_reg_int(odb, "-bpred:ras",
00192               "return address stack size (0 for no return stack)",
00193               &ras_size, /* default */ras_size,
00194               /* print */TRUE, /* format */NULL);
00195 
00196   opt_reg_int_list(odb, "-bpred:btb",
00197                    "BTB config (<num_sets> <associativity>)",
00198                    btb_config, btb_nelt, &btb_nelt,
00199                    /* default */btb_config,
00200                    /* print */TRUE, /* format */NULL, /* !accrue */FALSE);
00201 }

00285 {
00286   stat_reg_counter(sdb, "sim_num_insn",
00287                    "total number of instructions executed",
00288                    &sim_num_insn, sim_num_insn, NULL);
00289   stat_reg_counter(sdb, "sim_num_refs",
00290                    "total number of loads and stores executed",
00291                    &sim_num_refs, 0, NULL);
00292   stat_reg_int(sdb, "sim_elapsed_time",
00293                "total simulation time in seconds",
00294                &sim_elapsed_time, 0, NULL);
00295   stat_reg_formula(sdb, "sim_inst_rate",
00296                    "simulation speed (in insts/sec)",
00297                    "sim_num_insn / sim_elapsed_time", NULL);
00298 
00299   stat_reg_counter(sdb, "sim_num_branches",
00300                    "total number of branches executed",
00301                    &sim_num_branches, /* initial value */0, /* format */NULL);
00302   stat_reg_formula(sdb, "sim_IPB",
00303                    "instruction per branch",
00304                    "sim_num_insn / sim_num_branches", /* format */NULL);
00305 
00306   /* register predictor stats */
00307   if (pred)
00308     bpred_reg_stats(pred, sdb);
00309 }

00369 {
00370   /* nada */
00371 }

sim.h File Reference

Functions

Variables

Function Documentation

Variable Documentation


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