shared bus

• one possible design

  • we’ll revisit later when we talk about I/O

• tagged messages — everyone gets everything, filters

• contention if multiple communicators

  • some hardware enforces only one at a time

shared buses and caches

• remember caches?
• memory is pretty slow
• each CPU wants to keep local copies of memory

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• what happens when multiple CPUs cache same memory?

cache coherency states

• extra information for each cache block

  • overlaps with/replaces valid, dirty bits

• stored in each cache

• update states based on reads, writes and heard messages on bus

• different caches may have different states for same block

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• sample states:

  • Modified: cache has updated value
  • Shared: cache is only reading, has same as memory/others
  • Invalid

scheme 1: MSI

• blueblue: transition requires sending message on bus

• example: write while Shared

  • must send write — inform others with Shared state
  • then change to Modified

• example: hear write while Shared

  • change to Invalid
  • can send read later to get value from writer

• example: write while Modified

  • nothing to do — no other CPU can have a copy

MSI extensions

• extra states for unmodified values where no other cache has a copy

  • avoid sending ‘‘I am writing’’ message later

• allow values to be sent directly between caches

  • (MSI: value needs to go to memory first)

• support not sending invalidate/etc. messages to all cores

  • requires some tracking of what cores have each address
  • only makes sense with non-shared-bus design

using a shared the bus

• want to change a value other processors might have?
• use bus to tell them ‘‘get rid of your copy’’

  ---

• want to start using value other processor might have reserved?
• use bus to say ‘‘I’d like to use this value now’’

cache coherency states

• extra information for each cache block

  • overlaps with/replaces valid, dirty bits

• stored in each cache

• update states based on reads, writes and heard messages on bus

• different caches may have different states for same block

MSI scheme

• blueblue: transition requires sending message on bus

• example: write while Shared

  • must send write — inform others with Shared state
  • then change to Modified

• example: hear write while Shared

  • change to Invalid
  • can send read later to get value from writer

• example: write while Modified

  • nothing to do — no other CPU can have a copy

cache coherency exercise

• modified/shared/invalid; all initially invalid; 32B blocks, 8B read/writes

  • CPU 1: read 0x1000
  • CPU 2: read 0x1000
  • CPU 1: write 0x1000
  • CPU 1: read 0x2000
  • CPU 2: read 0x1000
  • CPU 2: write 0x2008
  • CPU 3: read 0x1008

• Q1: final state of 0x1000 in caches?

  • Modified/Shared/Invalid for CPU 1/2/3
  • CPU 1: CPU 2: CPU 3:

• Q2: final state of 0x2000 in caches?

  • Modified/Shared/Invalid for CPU 1/2/3
  • CPU 1: CPU 2: CPU 3:

cache coherency exercise solution

MSI extensions

• real cache coherency protocols sometimes more complex:

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• separate tracking modifications from whether other caches have copy
• send values directly between caches (maybe skip write to memory)
• send messages only to cores which might care (no shared bus)

scheme 2: MESI