+------------------- between cycles 0 and 1 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x0; loaded [30 f3 ce 0a 00 00 00 00 00 00 : irmovq $0xace, %rbx] +------------------- between cycles 1 and 2 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0xa; loaded [30 f0 01 00 00 00 00 00 00 00 : irmovq $0x1, %rax] +------------------- between cycles 2 and 3 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x14; loaded [62 00 : andq %rax, %rax] +------------------- between cycles 3 and 4 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x16; loaded [26 31 : cmovg %rbx, %rcx] because reg_srcA was set to 0 (%rax), set reg_outputA to 0x0 because reg_srcB was set to 0 (%rax), set reg_outputB to 0x0 +------------------- between cycles 4 and 5 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x18; loaded [24 32 : cmovne %rbx, %rdx] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0x0 because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xace) to register reg_dstE (3, which is %rbx) +------------------- between cycles 5 and 6 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1a; loaded [30 f0 ff ff ff ff ff ff ff ff : irmovq $0xffffffffffff, %rax] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0x1) to register reg_dstE (0, which is %rax) +------------------- between cycles 6 and 7 ----------------------+ | RAX: 1 RCX: 0 RDX: 0 | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x24; loaded [62 00 : andq %rax, %rax] wrote reg_inputE (0x1) to register reg_dstE (0, which is %rax) +------------------- between cycles 7 and 8 ----------------------+ | RAX: 1 RCX: 0 RDX: 0 | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x26; loaded [22 34 : cmovl %rbx, %rsp] because reg_srcA was set to 0 (%rax), set reg_outputA to 0x1 because reg_srcB was set to 0 (%rax), set reg_outputB to 0x1 wrote reg_inputE (0xace) to register reg_dstE (1, which is %rcx) +------------------- between cycles 8 and 9 ----------------------+ | RAX: 1 RCX: ace RDX: 0 | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x28; loaded [21 35 : cmovle %rbx, %rbp] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xace) to register reg_dstE (2, which is %rdx) +------------------- between cycles 9 and 10 ----------------------+ | RAX: 1 RCX: ace RDX: ace | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [63 00 : xorq %rax, %rax] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (0, which is %rax) +------------------- between cycles 10 and 11 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2c; loaded [23 36 : cmove %rbx, %rsi] because reg_srcA was set to 0 (%rax), set reg_outputA to 0xffffffffffffffff because reg_srcB was set to 0 (%rax), set reg_outputB to 0xffffffffffffffff wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (0, which is %rax) +------------------- between cycles 11 and 12 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: ace RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2e; loaded [25 37 : cmovge %rbx, %rdi] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xace) to register reg_dstE (4, which is %rsp) +------------------- between cycles 12 and 13 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: ace RSP: ace RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x30; loaded [30 f3 ad 0b 00 00 00 00 00 00 : irmovq $0xbad, %rbx] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xace) to register reg_dstE (5, which is %rbp) +------------------- between cycles 13 and 14 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: ace RSP: ace RBP: ace | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x3a; loaded [30 f0 01 00 00 00 00 00 00 00 : irmovq $0x1, %rax] wrote reg_inputE (0x0) to register reg_dstE (0, which is %rax) +------------------- between cycles 14 and 15 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: ace RSP: ace RBP: ace | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x44; loaded [62 00 : andq %rax, %rax] wrote reg_inputE (0xace) to register reg_dstE (6, which is %rsi) +------------------- between cycles 15 and 16 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: ace RSP: ace RBP: ace | | RSI: ace RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x46; loaded [22 31 : cmovl %rbx, %rcx] because reg_srcA was set to 0 (%rax), set reg_outputA to 0x0 because reg_srcB was set to 0 (%rax), set reg_outputB to 0x0 wrote reg_inputE (0xace) to register reg_dstE (7, which is %rdi) +------------------- between cycles 16 and 17 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: ace RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x48; loaded [23 32 : cmove %rbx, %rdx] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xace because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xbad) to register reg_dstE (3, which is %rbx) +------------------- between cycles 17 and 18 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x4a; loaded [30 f0 ff ff ff ff ff ff ff ff : irmovq $0xffffffffffff, %rax] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xbad because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0x1) to register reg_dstE (0, which is %rax) +------------------- between cycles 18 and 19 ----------------------+ | RAX: 1 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x54; loaded [62 00 : andq %rax, %rax] wrote reg_inputE (0x1) to register reg_dstE (0, which is %rax) +------------------- between cycles 19 and 20 ----------------------+ | RAX: 1 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x56; loaded [25 34 : cmovge %rbx, %rsp] because reg_srcA was set to 0 (%rax), set reg_outputA to 0x1 because reg_srcB was set to 0 (%rax), set reg_outputB to 0x1 +------------------- between cycles 20 and 21 ----------------------+ | RAX: 1 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x58; loaded [26 35 : cmovg %rbx, %rbp] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xbad because reg_srcB was set to f (none), set reg_outputB to 0x0 +------------------- between cycles 21 and 22 ----------------------+ | RAX: 1 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x5a; loaded [63 00 : xorq %rax, %rax] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xbad because reg_srcB was set to f (none), set reg_outputB to 0x0 wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (0, which is %rax) +------------------- between cycles 22 and 23 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x5c; loaded [22 36 : cmovl %rbx, %rsi] because reg_srcA was set to 0 (%rax), set reg_outputA to 0xffffffffffffffff because reg_srcB was set to 0 (%rax), set reg_outputB to 0xffffffffffffffff wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (0, which is %rax) +------------------- between cycles 23 and 24 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x5e; loaded [24 37 : cmovne %rbx, %rdi] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xbad because reg_srcB was set to f (none), set reg_outputB to 0x0 +------------------- between cycles 24 and 25 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x60; loaded [30 f3 00 00 00 00 00 00 00 00 : irmovq $0x0, %rbx] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xbad because reg_srcB was set to f (none), set reg_outputB to 0x0 +------------------- between cycles 25 and 26 ----------------------+ | RAX: ffffffffffffffff RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x6a; loaded [00 : halt] wrote reg_inputE (0x0) to register reg_dstE (0, which is %rax) +------------------- between cycles 26 and 27 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x6a; loaded [00 : halt] +------------------- between cycles 27 and 28 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x6a; loaded [00 : halt] +------------------- between cycles 28 and 29 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: bad RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x6a; loaded [00 : halt] wrote reg_inputE (0x0) to register reg_dstE (3, which is %rbx) +------------------- between cycles 29 and 30 ----------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: 0 RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x6a; loaded [00 : halt] +----------------------- halted in state: ------------------------------+ | RAX: 0 RCX: ace RDX: ace | | RBX: 0 RSP: ace RBP: ace | | RSI: ace RDI: ace R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +--------------------- (end of halted state) ---------------------------+