+------------------- between cycles    0 and    1 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x0; loaded [30 f0 03 00 00 00 00 00 00 00 : irmovq $0x3, %rax]
+------------------- between cycles    1 and    2 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xa; loaded [30 f3 ff ff ff ff ff ff ff ff : irmovq $0xffffffffffff, %rbx]
+------------------- between cycles    2 and    3 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x14; loaded [70 27 00 00 00 00 00 00 00 : jmp 0x27]
+------------------- between cycles    3 and    4 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x27; loaded [60 30 : addq %rbx, %rax]
+------------------- between cycles    4 and    5 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x29; loaded [70 1d 00 00 00 00 00 00 00 : jmp 0x1d]
because reg_srcA was set to 3 (%rbx), set reg_outputA to 0x0
because reg_srcB was set to 0 (%rax), set reg_outputB to 0x0
wrote reg_inputE (0x3) to register reg_dstE (0, which is %rax)
+------------------- between cycles    5 and    6 ----------------------+
| RAX:                3   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x1d; loaded [75 14 00 00 00 00 00 00 00 : jge 0x14]
wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (3, which is %rbx)
+------------------- between cycles    6 and    7 ----------------------+
| RAX:                3   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x14; loaded [70 27 00 00 00 00 00 00 00 : jmp 0x27]
+------------------- between cycles    7 and    8 ----------------------+
| RAX:                3   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x27; loaded [60 30 : addq %rbx, %rax]
wrote reg_inputE (0x2) to register reg_dstE (0, which is %rax)
+------------------- between cycles    8 and    9 ----------------------+
| RAX:                2   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x29; loaded [70 1d 00 00 00 00 00 00 00 : jmp 0x1d]
because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xffffffffffffffff
because reg_srcB was set to 0 (%rax), set reg_outputB to 0x2
+------------------- between cycles    9 and   10 ----------------------+
| RAX:                2   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x1d; loaded [75 14 00 00 00 00 00 00 00 : jge 0x14]
+------------------- between cycles   10 and   11 ----------------------+
| RAX:                2   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x14; loaded [70 27 00 00 00 00 00 00 00 : jmp 0x27]
+------------------- between cycles   11 and   12 ----------------------+
| RAX:                2   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x27; loaded [60 30 : addq %rbx, %rax]
wrote reg_inputE (0x1) to register reg_dstE (0, which is %rax)
+------------------- between cycles   12 and   13 ----------------------+
| RAX:                1   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x29; loaded [70 1d 00 00 00 00 00 00 00 : jmp 0x1d]
because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xffffffffffffffff
because reg_srcB was set to 0 (%rax), set reg_outputB to 0x1
+------------------- between cycles   13 and   14 ----------------------+
| RAX:                1   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x1d; loaded [75 14 00 00 00 00 00 00 00 : jge 0x14]
+------------------- between cycles   14 and   15 ----------------------+
| RAX:                1   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x14; loaded [70 27 00 00 00 00 00 00 00 : jmp 0x27]
+------------------- between cycles   15 and   16 ----------------------+
| RAX:                1   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x27; loaded [60 30 : addq %rbx, %rax]
wrote reg_inputE (0x0) to register reg_dstE (0, which is %rax)
+------------------- between cycles   16 and   17 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x29; loaded [70 1d 00 00 00 00 00 00 00 : jmp 0x1d]
because reg_srcA was set to 3 (%rbx), set reg_outputA to 0xffffffffffffffff
because reg_srcB was set to 0 (%rax), set reg_outputB to 0x0
+------------------- between cycles   17 and   18 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x1d; loaded [75 14 00 00 00 00 00 00 00 : jge 0x14]
+------------------- between cycles   18 and   19 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x14; loaded [70 27 00 00 00 00 00 00 00 : jmp 0x27]
+------------------- between cycles   19 and   20 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x27; loaded [60 30 : addq %rbx, %rax]
wrote reg_inputE (0xffffffffffffffff) to register reg_dstE (0, which is %rax)
+------------------- between cycles   20 and   21 ----------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x26; loaded [00 : halt]
+------------------- between cycles   21 and   22 ----------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x26; loaded [00 : halt]
+------------------- between cycles   22 and   23 ----------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x26; loaded [00 : halt]
+------------------- between cycles   23 and   24 ----------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x26; loaded [00 : halt]
+------------------- between cycles   24 and   25 ----------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x26; loaded [00 : halt]
+----------------------- halted in state: ------------------------------+
| RAX: ffffffffffffffff   RCX:                0   RDX:                0 |
| RBX: ffffffffffffffff   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+--------------------- (end of halted state) ---------------------------+