+------------------- between cycles 0 and 1 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x0; loaded [30 f2 07 00 00 00 00 00 00 00 : irmovq $0x7, %rdx] +------------------- between cycles 1 and 2 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0xa; loaded [30 f1 03 00 00 00 00 00 00 00 : irmovq $0x3, %rcx] +------------------- between cycles 2 and 3 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x14; loaded [60 13 : addq %rcx, %rbx] +------------------- between cycles 3 and 4 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x16; loaded [61 21 : subq %rdx, %rcx] because reg_srcA was set to 1 (%rcx), set reg_outputA to 0x0 because reg_srcB was set to 3 (%rbx), set reg_outputB to 0x0 +------------------- between cycles 4 and 5 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x18; loaded [62 23 : andq %rdx, %rbx] because reg_srcA was set to 2 (%rdx), set reg_outputA to 0x0 because reg_srcB was set to 1 (%rcx), set reg_outputB to 0x0 wrote reg_inputE (0x7) to register reg_dstE (2, which is %rdx) +------------------- between cycles 5 and 6 ----------------------+ | RAX: 0 RCX: 0 RDX: 7 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1a; loaded [63 12 : xorq %rcx, %rdx] because reg_srcA was set to 2 (%rdx), set reg_outputA to 0x7 because reg_srcB was set to 3 (%rbx), set reg_outputB to 0x0 wrote reg_inputE (0x3) to register reg_dstE (1, which is %rcx) +------------------- between cycles 6 and 7 ----------------------+ | RAX: 0 RCX: 3 RDX: 7 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1c; loaded [62 26 : andq %rdx, %rsi] because reg_srcA was set to 1 (%rcx), set reg_outputA to 0x3 because reg_srcB was set to 2 (%rdx), set reg_outputB to 0x7 wrote reg_inputE (0x3) to register reg_dstE (3, which is %rbx) +------------------- between cycles 7 and 8 ----------------------+ | RAX: 0 RCX: 3 RDX: 7 | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [00 : halt] because reg_srcA was set to 2 (%rdx), set reg_outputA to 0x7 because reg_srcB was set to 6 (%rsi), set reg_outputB to 0x0 wrote reg_inputE (0xfffffffffffffffc) to register reg_dstE (1, which is %rcx) +------------------- between cycles 8 and 9 ----------------------+ | RAX: 0 RCX: fffffffffffffffc RDX: 7 | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [00 : halt] wrote reg_inputE (0x3) to register reg_dstE (3, which is %rbx) +------------------- between cycles 9 and 10 ----------------------+ | RAX: 0 RCX: fffffffffffffffc RDX: 7 | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [00 : halt] wrote reg_inputE (0xfffffffffffffffb) to register reg_dstE (2, which is %rdx) +------------------- between cycles 10 and 11 ----------------------+ | RAX: 0 RCX: fffffffffffffffc RDX: fffffffffffffffb | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [00 : halt] wrote reg_inputE (0x0) to register reg_dstE (6, which is %rsi) +------------------- between cycles 11 and 12 ----------------------+ | RAX: 0 RCX: fffffffffffffffc RDX: fffffffffffffffb | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [00 : halt] +----------------------- halted in state: ------------------------------+ | RAX: 0 RCX: fffffffffffffffc RDX: fffffffffffffffb | | RBX: 3 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +--------------------- (end of halted state) ---------------------------+