+------------------- between cycles    0 and    1 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0x0; loaded [30 f4 04 00 00 00 00 00 00 00 : irmovq $0x4, %rsp]
+------------------- between cycles    1 and    2 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xa; loaded [b0 0f : popq %rax]
+------------------- between cycles    2 and    3 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xc; loaded [00 : halt]
because reg_srcA was set to 4 (%rsp), set reg_outputA to 0x0
because reg_srcB was set to 4 (%rsp), set reg_outputB to 0x0
+------------------- between cycles    3 and    4 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xc; loaded [00 : halt]
+------------------- between cycles    4 and    5 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xc; loaded [00 : halt]
wrote reg_inputE (0x4) to register reg_dstE (4, which is %rsp)
because mem_readbit was 1, set mem_output to 0xfb0000000000000 by reading memory from mem_addr (0x4)
+------------------- between cycles    5 and    6 ----------------------+
| RAX:                0   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                4   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xc; loaded [00 : halt]
wrote reg_inputE (0xc) to register reg_dstE (4, which is %rsp)
wrote reg_inputM (0xfb0000000000000) to register reg_dstM (0, which is %rax)
+------------------- between cycles    6 and    7 ----------------------+
| RAX:  fb0000000000000   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                c   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+-----------------------------------------------------------------------+
pc = 0xc; loaded [00 : halt]
+----------------------- halted in state: ------------------------------+
| RAX:  fb0000000000000   RCX:                0   RDX:                0 |
| RBX:                0   RSP:                c   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14:                0 |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
+--------------------- (end of halted state) ---------------------------+