+------------------- between cycles 0 and 1 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x0; loaded [30 f4 00 01 00 00 00 00 00 00 : irmovq $0x100, %rsp] +------------------- between cycles 1 and 2 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0xa; loaded [30 f3 20 00 00 00 00 00 00 00 : irmovq $0x20, %rbx] +------------------- between cycles 2 and 3 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x14; loaded [40 34 00 00 00 00 00 00 00 00 : rmmovq %rbx, 0x0(%rsp)] +------------------- between cycles 3 and 4 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1e; loaded [90 : ret] because reg_srcA was set to 3 (%rbx), set reg_outputA to 0x0 because reg_srcB was set to 4 (%rsp), set reg_outputB to 0x0 +------------------- between cycles 4 and 5 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1f; loaded [00 : halt] because reg_srcA was set to 4 (%rsp), set reg_outputA to 0x0 because reg_srcB was set to 4 (%rsp), set reg_outputB to 0x0 wrote reg_inputE (0x100) to register reg_dstE (4, which is %rsp) +------------------- between cycles 5 and 6 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 100 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1f; loaded [00 : halt] wrote reg_inputE (0x20) to register reg_dstE (3, which is %rbx) because mem_writebit was 1, set memory at mem_addr (0x100) to mem_input (0x20) +------------------- between cycles 6 and 7 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 100 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x1f; loaded [00 : halt] because mem_readbit was 1, set mem_output to 0x20 by reading memory from mem_addr (0x100) +------------------- between cycles 7 and 8 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 100 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x20; loaded [30 f0 02 01 00 00 00 00 00 00 : irmovq $0x102, %rax] wrote reg_inputE (0x108) to register reg_dstE (4, which is %rsp) +------------------- between cycles 8 and 9 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [00 : halt] +------------------- between cycles 9 and 10 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [00 : halt] +------------------- between cycles 10 and 11 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [00 : halt] +------------------- between cycles 11 and 12 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [00 : halt] wrote reg_inputE (0x102) to register reg_dstE (0, which is %rax) +------------------- between cycles 12 and 13 ----------------------+ | RAX: 102 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x2a; loaded [00 : halt] +----------------------- halted in state: ------------------------------+ | RAX: 102 RCX: 0 RDX: 0 | | RBX: 20 RSP: 108 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +--------------------- (end of halted state) ---------------------------+