From: Charles Grassl (
Date: Mon Nov 11 1991 - 20:48:52 CST

Hello John;

I noticed the high SAXPY bandwidth for the CM-2 in your stream data
table. Andrew Zackary brought this to my attention and also told me of
his correspondence with you.

As each FPU in the CM-2 has one 32-bit wide path to memory, the peak
bandwidth would seem to be 7 MHz * 2000 CPUs * 4 Bytes, or 56,000
Mbyte/sec. Do you know if the report 80593 Mbyte/sec is genuine or how
it was attained?

Also, I noted your entry for the NEC SX-3/14. The SX-3/14 has a major clock
period of 5.8 nanoseconds (172 MHz) and a minor clock period of 2.9
nanoseconds (345 MHz). The memory ports operate at 345 MHz in vector

The SX-3/14 bandwidth seems rather low. Two CPUs share three 256-bit
wide memory ports. I do not know if these 256-bit wide ports go all
the way to shared memory, or if they go to another level of caching,
like in an IBM system. Do you know much about the memory


Charles M. Grassl
Cray Research, Inc.
(612) 683-3531

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