Sorry for my mistake in my last posting.
In article <1993Jul16.email@example.com> firstname.lastname@example.org (Toshinori Maeno) writes:
>My measurement for TITAN2-400 (Alpha 133MHz) tells,
> 1. read miss penalty is 8 cycles for read, 12 cycles for write for the
34 is correct
>first level cache when the data is in the second level cache.
> 2. read miss penalty is 12 cycles for read, 40 cycles for write when
>the data is only in the memory.
Tokyo Institute of Technology
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