CS 3330

CS 3330: Undergraduate Computer Architecture

Lecture Time/Location: Tu/Th 11am-12:15pm @ Olsson 120
Lab-1 Time/Location: We 3:30pm-4:45pm @ Olsson 018
Lab-2 Time/Location: We 5:00pm-6:15pm @ Olsson 005

The goal of this course is to introduce students to the hardware/software interface and the fundamental building blocks that make up a modern computer. By taking this course, students will:

become conversant with fundamental computer architecture concepts,
be able to read and evaluate specs of modern architectures,
understand the implications of computer architecture on performance and security, and
gain experience designing a working processor from scratch.

Required Textbook:

Other textbooks and online resources:

Graduate textbook:Hennessy and Patterson, "Computer Architecture: A Quantitative Approach", Sixth Edition
Books from Synthesis Lectures on Computer Architecture

Contact

Instructor:

Ashish Venkat

Teaching Assistants:

Grading

The grading breakdown for this course is:

5%: Peer Review and Professionalism
20%: 5 homework assignments
15%: Project-1 (Feb 9 to Apr 12, with a checkpoint due on Mar 15)
10%: Project-2 (Apr 19 to May 3)
10%: Midterm exam-1 on Feb 24 (will include material from Jan 25 to Feb 10)
15%: Midterm exam-2 on Apr 7 (will include material from Feb 15 to Mar 24)
25%: Final exam on May 13 from 9am-12pm (inclusive of all material)

We will NOT use an absolute grading scale for this course. Your final letter grades will be assigned based on your overall performance, relative to the class average. In addition, you will receive an automatic level-up in your letter grade (e.g., A- to A) if you ace the final exam. You will be periodically notified of your standings.

Assignments

There will be 5 homework assignments (due roughly every two weeks). Each homework assignment will involve 5-6 exercise problems from the textbook. Links to assignments:

HW1 -- Quantitative Analysis and Instruction Set Architecture [Solutions]
HW2 -- Digital Logic and Single-Cycle Processors [Solutions]
HW3 -- Pipelined Datapath and Control [Solutions]
HW4 -- Branch Prediction and OOO Processors [Solutions]
HW5 -- Cache Organization and Management [Solutions]

There will also be 2 lab projects that will involve building a processor and a cache side-channel exploit from scratch.

Project-1 -- Processor Design
Project-2 -- Cache Attacks

Guidelines and Policies:

You will work in groups of three students for all assignments (including the lab projects) and all students will receive the same grade. In addition, each individual member will be given a chance to evaluate other members of the group for every assignment/project.
Homework assignments are to be turned in electronically on Gradescope, at the beginning of the lecture, unless otherwise noted.
You are strongly encouraged to typeset your homework solutions, but not strictly required.
Homework assignments are primarily intended for practice, rather than assessment. No single problem will have a significant impact on your final grade.
Solutions to homework assignments will be typically released 2 days after the assignment is due.
Late assignments are not encouraged. Late assignments turned in before solutions are posted will be assessed a flat 10% (of the maximum score) late penalty. If you turn in the assignment after the solutions have been posted, it will not be accepted.

Schedule

Week	Date	Topic	Assignment
Week 1	Jan 20	Introduction, Motivation, and Course Logistics Background Preparation: Appendix A	-
Week 2	Jan 25	Instruction Set Architecture Reading: Chapters 1.3, 2.2, 2.3, 2.5	HW1 out
	Jan 26	Discussion: ISA
	Jan 27	Memory Organization and Control Flow Reading: Chapters 2.6, 2.7, 2.8	-
Week 3	Feb 1	Quantitative Analysis in Computer Architecture Reading: Chapters 1.6 and 1.10	-
	Feb 2	Discussion: Quantitative Analysis and Digital Logic
	Feb 3	Design of the MIPS Arithmetic and Logic Unit Reading: Appendix B.2, B.3, and B.5	-
Week 4	Feb 8	Design of the Control Unit and Register File Reading: Appendix B.7, B.8, and Chapter 4.3	HW1 due, HW2 out
	Feb 9	Discussion: Introduction to Project-1	Project-1 out
	Feb 10	The MIPS Single Cycle Processor Architecture Reading: Chapters 4.3 and 4.4	-
Week 5	Feb 15	Pipelined Datapath and Control Reading: Chapters 4.5 and 4.6	-
	Feb 16	Discussion: Single-Cycle Processor
	Feb 17	Pipelining: Data Hazards Reading: Chapter 4.7	-
Week 6	Feb 22	Midterm Exam-1 Review	HW2 due
	Feb 23	Discussion: Midterm Exam-1 Review
	Feb 24	Midterm Exam-1	-
Week 7	Mar 1	Pipelining: Forwarding Reading: Chapter 4.7	HW3 out
	Mar 2	Discussion: Pipelining
	Mar 3	Pipelining: Control Hazards Reading: Chapter 4.8	-
Spring Break
Week 8	Mar 15	Branch Prediction Reading: Chapters 4.8 and 4.10	Project-1 Checkpoint due
	Mar 16	Discussion: Control Hazards and Branch Prediction
	Mar 17	Superscalar Execution and Static Scheduling Reading: Chapter 4.10	HW3 due, HW4 out
Week 9	Mar 22	Data-Level Parallelism Reading: Chapters 6.2 and 6.3	-
	Mar 23	Discussion: Branch Prediction and Superscalars
	Mar 24	Out-Of-Order Execution Reading: Chapter 4.11	-
Week 10	Mar 29	Introduction to Memory Hierarchy: Cache Fundamentals Reading: Appendix B.9 and Chapter 5.3	-
	Mar 30	Discussion: OOO Superscalars and Caches
	Mar 31	Cache Organization and Design Reading: Chapter 5.4	HW4 due
Week 11	Apr 5	Midterm Exam-2 Review	-
	Apr 6	Discussion: Midterm Exam-2 Review
	Apr 7	Midterm Exam-2	-
Week 12	Apr 12	Cache Management and Policies Reading: Chapter 5.8	Project-1 due, HW5 out
	Apr 13	Discussion: Cache Organization and Management
	Apr 14	Cache Optimizations and Side-Channel Attacks Reading: Chapters 8.1-8.5 from Principles of Secure Processor Architecture Design	-
Week 13	Apr 19	Cache Side-Channel Attacks Reading: Chapters 8.1-8.5 from Principles of Secure Processor Architecture Design	Project-2 out
	Apr 20	Discussion: Project-1 Interviews
	Apr 21	Virtual Memory: Page Tables and TLBs Reading: Chapter 5.7	-
Week 14	Apr 26	Virtual Memory: Page Fault Handling and Virtual Caches Reading: Chapter 5.7	-
	Apr 27	Discussion: Virtual Memory
	Apr 28	In-Class Hacking Workshop	HW5 due
Week 15	May 3	Final Review	Project-2 due

Honor Code

I trust every student in this course to fully abide by the University's Honor Code and pledge to not commit academic fraud. You are allowed to discuss, collaborate, and brainstorm both within and outside your group. However, you're not allowed to plagiarize solutions/text from another student's assignment or from the internet. Cheating will be taken seriously and will be reported to the honor committee. All suspected honor violations will receive an failing grade for the course regardless of any action taken by the Honor Committee.

Please let me know if you have any questions regarding the course Honor policy. If you believe you may have committed an Honor Offense, you may wish to file a Conscientious Retraction by calling the Honor Offices at (434) 924-7602. For your retraction to be considered valid, it must, among other things, be filed with the Honor Committee before you are aware that the act in question has come under suspicion by anyone. More information can be found here. Your Honor representatives can be found at this link

Learning Accommodations

Students with disabilities or learning needs
It is my goal to create a learning experience that is as accessible as possible. If you anticipate any issues related to the format, materials, or requirements of this course, please meet with me outside of class so we can explore potential options. Students with disabilities may also wish to work with the Student Disability Access Center to discuss a range of options to removing barriers in this course, including official accommodations. Please visit their website for information on this process and to apply for services online. If you have already been approved for accommodations through SDAC, please send me your accommodation letter and meet with me so we can develop an implementation plan together.

Discrimination and power-based violence
The University of Virginia is dedicated to providing a safe and equitable learning environment for all students. To that end, it is vital that you know two values that I and the University hold as critically important:

Power-based personal violence will not be tolerated.
Everyone has a responsibility to do their part to maintain a safe community on Grounds.

If you or someone you know has been affected by power-based personal violence, more information can be found on the UVA Sexual Violence website that describes reporting options and resources available.

As your professor and as a person, know that I care about you and your well-being and stand ready to provide support and resources as I can. As a faculty member, I am a responsible employee, which means that I am required by University policy and federal law to report what you tell me to the University's Title IX Coordinator. The Title IX Coordinator's job is to ensure that the reporting student receives the resources and support that they need, while also reviewing the information presented to determine whether further action is necessary to ensure survivor safety and the safety of the University community. If you wish to report something that you have seen, you can do so at the Just Report It portal. The worst possible situation would be for you or your friend to remain silent when there are so many here willing and able to help.

Religious accommodations
It is the University's long-standing policy and practice to reasonably accommodate students so that they do not experience an adverse academic consequence when sincerely held religious beliefs or observances conflict with academic requirements. Students who wish to request academic accommodation for a religious observance should submit their request in writing directly to me as far in advance as possible. Students who have questions or concerns about academic accommodations for religious observance or religious beliefs may contact the University’s Office for Equal Opportunity and Civil Rights (EOCR) at UVAEOCR@virginia.edu or (434) 924-3200.