CS3130 Fall 2024 quizzes



quiz for week 2

Question 1 (4 pt; mean 3.64)

Consider the following C snippet running on a system with 8-byte pointers and 8-byte longs:

long A[4] = {10, 20, 30, 40};
long B[4] = {50, 60, 70, 80};
long *C[2] = {&A[1], &B[2]};
long *D[2] = {&A[1], &B[2]};
B[2] = *C[1];
C[1] = &A[3];
*C[0] = B[0];

The arrays C and D contains addresses. Depending on where the arrays are stored in memory the values of the addresses in C and D will vary. For example, if A is located at address 0x1000 and B at 0x2000, then D[0] could contain 0x1008 and D[1] will contain 0x2010, but these values would be different if A and B were at different locations.

For some placement of the arrays in memory, which of the following are possible values for the array C at the end of the code snippet above? Select all that apply.

C[0] = &A[1], C[1] = &A[3]

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Consider the following Makefile:

a: b e
    buildA

b: c
    buildB

c: d f
    buildC

Assume:

Question 2 (4 pt; mean 3.91) (see above)

Which of the following should always cause buildB to run? Select all that apply.

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Question 3 (4 pt; mean 3.06) (see above)

Changing the line a: b e to a: b e c in the Makefile would ____.

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Suppose a C project has the following source files:

From these two programs foo and bar is built using the following sequence of commands:

clang -Wall -g -Og -c foo.c -o foo.o
clang -Wall -g -Og -c bar.c -o bar.o
clang -Wall -g -Og -c common.c -o common.o
clang -Wall -g -Og -o bar bar.o common.o
clang -Wall -g -Og -o foo foo.o common.o
Question 4 (4 pt; mean 3.96) (see above)

If bar.h is modified which command or commands should be rerun to handle these modifications? Select all that apply.

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Consider the directory hierarchy

    foo/bar/baz

assuming that foo, bar, and baz are directories) and they have the following ownership (user ID), group ID, and permissions (represented in octal):

Users 612 and 1219 are both members of group 75, so all their processes run with that group ID.

Question 5 (4 pt; mean 3.92) (see above)

Which of the following commands will fail due to a permission error (assuming that the commands are issued from the parent directory of foo)? Select all that apply.

  1. assuming user 613 is also a member of group 75

  2. assuming user 613 is also a member of group 75

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Question 6 (4 pt; mean 3.74)

The kill command-line utility invokes the kill system call, which can be used, among other things, to make another process terminate. When a user runs kill to terminate another process using its process ID, at what point(s) does the processor switch into kernel (privileged) mode? Select all that apply.

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quiz for week 3

Suppose the following happens in the following order on a single-processor/single-core Unix-like system. Initially, process A has been running (and using the processor) for a while. Then it is context switched and B is now running on the CPU. Then, the following stesp happen:

  1. the user who is running process B presses control-C, which runs a signal handler in process B
  2. process B's signal handler prints a message to the screen
  3. process B exits its signal handler and the function that was running before in process B resumes
  4. process B starts to read a file, but the file's data is not yet available
  5. while process B is waiting, process A resumes its computation
Question 1 (4 pt; mean 3.5) (see above)

A handler for an exception other than a system call will start running ____. Select all that apply.

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Question 2 (4 pt; mean 3.63) (see above)

A handler for a system call will start running ___. Select all that apply.

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Suppose a single-core (single-processor) x86-64 system is running three processes X, Y, and Z. Each process has a single thread.

Initially, process X is doing computations on the first core, process Y is waiting for keyboard input. Process Z is in the middle of computations, but was stopped by the OS as a result of a timer earlier and will be resumed by the OS at some point in the future.

Question 3 (3 pt; mean 2.88) (see above)

Initially, the value of the general purpose register %rax for process X is stored ____.

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Question 4 (3 pt; mean 2.83) (see above)

Initially, the value of the general purpose register %rax for process Z is stored ____.

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Question 5 (4 pt; mean 3.14) (see above)

Suppose after a keypress occurs, process Y starts running immediately. Between when the keypress occurs and when process Y resumes running, ____. Select all that apply.

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Suppose two processes, one with PID 1000 and one with PID 2001 are running the same program and both running as the same user. In both processes, the function handle_usr1 below is setup as a signal handler for SIGUSR1 and handle_usr2 is setup as a signal handler for SIGUSR2:

void handle_usr1(int signum) {
    write(STDOUT_FILENO, "A", 1);
    kill(2001, SIGKILL);
}

void handle_usr2(int signum) {
    write(STDOUT_FILENO, "B", 1);
    kill(1000, SIGUSR1)
    write(STDOUT_FILENO, "C", 1);
}

Assume all relevant header files are included and that no other code in the program will write output or cause the programs to exit.

write(STDOUT_FILENO, "X", 1) outputs the character X to stdout.

Question 6 (5 pt; mean 4.48) (see above)

If SIGUSR2 is sent to PID 2001, which of the following are possible outcomes? Select all that apply.

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quiz for week 4

Question 1 (5 pt; mean 4.04)

Consider the following C function:

int count = 0; pid_t pid;
pid_t mystery() {
    for (int i = 0; i < 4; ++i) {
        count += 1;
        pid = fork();
        if (pid != 0) {
            return pid;
        }
    }
    return 0;
}

Which of the following is true about the above function? Select all that apply.

  1. strictly speaking only one process is created by the original process and its pid is returned in the original process, so using waitpid to retrieve it status information is easy. (Even if it wasn't returned, we can call waitpid() with a pid of -1 to wait for all children.) Some students interpreted "all the processes it creates" as including indirectly created processes, which wasn't our intention

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Consider the following C snippet (which uses the POSIX API):

int output_fd = open("output.txt", O_WRONLY | O_CREAT);
if (output_fd < 0)
    handle_error();
pid_t pid = fork();
dup2(output_fd, STDOUT_FILENO);
if (pid == 0) {
    const char *argv[] = {"./a.out", NULL};
    execv("./a.out", argv);
} else if (pid > 0) {
    int status;
    close(output_fd);
    if ((pid_t) -1 == waitpid(pid, &status, 0)) {
        handle_error();
    }
    printf("finished running a.out\n");
}

For the following questions, assume that this program is not called a.out, and that open, fork, dup2, execv, close and waitpid do not fail.

This code probably intended to run a program called a.out, sending its output to output.txt. It succeeds at this but has some bugs.

Question 2 (4 pt; mean 3.72) (see above)

The author the above code is surprised to find that the message finished running a.out from the printf is not visible even though a.out runs and terminates. What is the most likely reason why this is this happening?

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Question 3 (4 pt; mean 3.9) (see above)

If STDOUT_FILENO were changed to STDIN_FILENO in the above program, then ____. Select all that apply. *

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Question 4 (4 pt; mean 3.18)

Which of these items are copied into the child process on a fork()? Assume copy-on-write is NOT implemented. Choose all that apply.

  1. True if we mean the file descriptor table; not true if we mean the open file descriptions

  2. need new mappings since process will have freshly allocated physical memory.

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Question 5 (3 pt; mean 2.89)

Now imagine the following pseudocode in some process that starts out with default stdout (pointing to the screen):

 fd1 = open(file1, ...)
 close(STDOUT_FILENO)
 fd2 = open(file2, ...)
 fd3 = dup2(fd2,STDOUT_FILENO)
 write(STDOUT_FILENO, ...)

Where will the write appear?

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Question 6 (5 pt; mean 4.78)

Consider the following code snippets:

program1:

int x = 0; pid_t childpid = -1, mypid; 

childpid = fork();
if (childpid > 0) {
  x=500;
  printf(“%d forked,”, childpid);
  waitpid(childpid, etc);
  printf(“%d done,”, childpid);
}
else if (childpid == 0) {
  mypid = getpid();
  x=100;
  printf(“%d exec’ing,”, mypid);
  char *args[] = {"program2", "0", NULL};
  exec(program2, args);
  printf(“%d post-exec,”, mypid);
}

program2:

int x; 

int main(int argc, char**argv) {
  x = strtoi(argv[1]);
  if (x == 0) {
    x++;
    char *args[] = {"program2", itoa(x), NULL};
    exec(program2, args);
  }
  printf(“x=%d,”, x);
  return 0;
}

Which, if any, of the following outputs sequences are valid, assuming the child pid is 23 and the fork and execs do not fail? Select all that apply.

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quiz for week 5

Question 1 (4 pt; mean 3.9)

The following process operates on a file that contains the following lines:

LINE1
LINE2
LINE3

Consider the following code snippet (the read consumes 6 characters because of the newline at the end of each line):

int retval;

pid_t childpid = fork();
if (childpid > 0) {
  char buf[1024];
  fd1 = open("file", O_RDWR);
  retval = read(fd1, buf, 6);
  write(STDOUT, buf, 6);
} else if (childpid == 0) {
  char buf[1024];
  fd1 = open("file", O_RDWR);
  fd2 = dup(fd1);
  retval = read(fd1, buf, 6);
  retval = read(fd2, buf+6, 6);
  write(STDOUT, buf, 12);
}

Assume the file exists and the fork and the reads and writes succeed.

Which of the following outputs, if any, are possible (newlines are omitted to make the options easier to read)? Choose all that apply.

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Consider a system with a virtual memory system with:

Question 2 (4 pt; mean 3.87) (see above)

If one wanted to modify this system to support 17 bit virtual addresses without changing the size of pages or physical page numbers, then the number of entries in the resulting page table would be _____ (instead of 128 now). If it is not possible to increase the virtual address size this way while not changing the size of pages or physical addresses, write "impossible". If not enough infomation is given, write "unknown" and explain in the comments.

Answer:
Key: 512
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Consider a system with 512-byte pages and the following page table:

virtual page number valid physical page number read allowed? write allocated? execute allocated? user mode access allowed?
0x00
0x110x121011
0x210x341011
0x310x121101
0x410x311101
0x50
0x610x3a1101
0x710x041101
Question 3 (4 pt; mean 3.44) (see above)

Give an example of two different virtual addresses which would both map to the same physical address. Write your answer as two hexadecimal numbers separated by a comma. If this is not possible write "impossible".

Answer:
Key: one address in VP 1, one in VP 3 (to be graded manually)
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Question 4 (4 pt; mean 3.57) (see above)

If a process is running using the page table above, what would be an appropriate address for its stack pointer to be set to?

Answer:
Key: something in virtual page 4 or 6 or 7 or 3
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Question 5 (4 pt; mean 3.37)

Consider a system with

A program accesses virtual address 0x98765 which corresponds to physical address 0xa8765 and is writeable, not executable, and user-mode accessible. As part of this access, the processor accesses a pagetable entry at address ____. Write your answer as a hexadecimal number. If not enough information is given, write "unknown".

Answer:
Key: 0x12984
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Question 6 (4 pt; mean 3.7)

Suppose a process running on a system with 4096-byte pages has the following memory layout:

Assume the system running the program uses copy-on-write in a way which copies as few pages as possible. Initially, the program is running with all pages mapped in its memory so it can access any of its memory without an exception occuring (including writing).

Then the following happens in this order:

As a result of these events, how many additional pages of memory will be allocated to store the program's memory? (Do not include space for page tables, operating system bookkeeping, etc.)

Answer:
Key: 1 (stack, 0xa6000; only one copy needed for both writes) + 8 (heap, child) = 9
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quiz for week 6

Question 1 (4 pt; mean 3)

If one doubles the size of pages and also doubles number of entries in each page table on a system with five-level page tables, this will add ___ bits to the size of virtual addresses supported.

If the address size supported will increase, write a positive number; if it will descrease, write a negative number; if it will stay the same write "0". If not enough information is provided, write "unknown" and explain in the comments.

Answer:
Key: 6
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Consider a system which uses three-level page tables with:

Question 2 (4 pt; mean 2.85) (see above)

If a program accesses virtual address 0x12345678, and the page table base register is set to 0x10000, then it will access a first-level page table entry at address ____. Write your answer as a hexadecimal number.

Answer:
Key: 0x10010
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Question 3 (4 pt; mean 2.25) (see above)

As a result of the first-level page table access of the previous question, the system accesses a second-level page table entry at address 0x2011a. What is a possible value of the first-level page table entry that was accessed? Write your answer as a hexadecimal integer.

If it was impossible for a second-level page table entry at this address to have been accessed, write "impossible" and explain in the comments. If not enough information was provided, write "unknown" and explain what additional information would be needed and how the answer would be computed given that.

Answer:
Key: impossible

was originally miskeyed because we miscomputed the second-level page table entry address

this address is not a multiple of 4, but any computed page table entry address will be

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Question 4 (4 pt; mean 2.16) (see above)

Suppose a process on this system can access exactly five virtual pages without exceptions occuring:

  • virtual page number 0x00000f (addresses 0x3c00-0x3fff)
  • virtual page number 0x000010 (addresses 0x4000-0x43ff)
  • virtual page number 0x00010f (addresses 0x43c00-0x43fff)
  • virtual page number 0x000112 (addresses 0x44800-0x44bff)
  • virtual page number 0xff00ff (addresses 0x3fc03fc00-0x3fc03ffff)

Since this system uses multi-level page tables, the process will need to have multiple page tables (one at the first-level, plus one or more second-level and/or third-level page tables) allocated ot make this poossible. How many total page tables (across all levels) must be allocated for the process?

Answer:
Key: 6

1 first-level, 2 second-level, 3 third-level = 6

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Consider the following C snippet:

for (int i = 0; i < SIZE; i += 1) {
    for (int j = 0; j < SIZE; j += 1) {
        A[i] = A[i] + B[i * 4] * C[j * SIZE + i];
    }
}
Question 5 (3 pt; mean 2.45) (see above)

Which of the following changes would improve the spatial locality of the code? (Some of these changes will change the values computed by the code.) Select all that apply.

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Suppose a direct-mapped cache (with 4 sets and 4-byte blocks) has the following contents:

set indextag (written in binary)validdata bytes (in hexadecimal; lowest address first)
00
11101102 FF 41 02
21111101 11 23 45
31000133 55 77 9A
Question 6 (4 pt; mean 3.75) (see above)

The original memory address of the byte stored in the cache with value of 0xFF is ____. Write your answer as a hexadecimal number.

Answer:
Key: 1101[tag] 01[index] 01[offset] = 11010101 = 0xd5
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Question 7 (3 pt; mean 2.83) (see above)

Reading a byte from address with tag 1111, set index 3, and offset 2 would ___. Assume that if the value is not present in the cache already, it will be loaded into the cache. Select all that apply.

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quiz for week 7

Suppose a 2-way set associative cache (with 4 sets and 4-byte blocks and LRU replacement policy) has the following contents:

way 0way 1
set indextag (written in binary)validdata bytes (in hexadecimal; lowest address first) tag (written in binary)validdata bytes (in hexadecimal; lowest address first)LRU
00 0 0
10001102 FF 41 02 0 1
21011101 11 23 45 0011199 AA BB CC 0
31000133 55 77 9A 00111FF 00 FE 01 1
Question 1 (4 pt; mean 3.87) (see above)

Reading a byte from an address with tag 1000, index 2, offset 3 would ____. Select all that apply.

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Consider a direct-mapped data cache with

and a C array declared as follows:

int array[1024];

where the array starts on an address that is a multiple of 16384 on a system where ints take up 4 bytes and virtual memory is not in use.

Note that based on the description above:

Question 2 (4 pt; mean 3.94) (see above)

Consider the following loop:

for (int outer = 0; outer < 1000; outer += 1) {
    array[0] += 1;
    array[2] += 1;
    array[4] += 1;
}

If only the accesses to array use the data cache, the data cache is initially empty, and the compiler does not optimize away any accesses to array, how many cache misses will occur?

Answer:
Key: 2
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Question 3 (4 pt; mean 3.31) (see above)

Consider the following loop:

for (int outer = 0; outer < 1000; outer += 1) {
    array[0] += 1;
    array[9] += 1;
    array[18] += 1;
    array[27] += 1;
    array[36] += 1;
    array[45] += 1;
    array[54] += 1;
    array[63] += 1;
    array[72] += 1;
}

If only the accesses to array use the data cache, the data cache is initially empty, and the compiler does not optimize away any accesses to array, how many cache misses will occur?

Answer:
Key: 2007

2007

(originally miskeyed because I forgot about 54

relevant mappings of array indices to sets: set 0: 0-3, set 2: 8-11 AND 72-75, set 4: 16-19; set 6: 25-28; set 9: 36-39; set 11: 44-47; set 13: 52--55 set 15: 60-63;

so 7 misses for sets 0 (array[0]), 4 (array[18]), 6 (array[27]), 9 (array[36]), 11 (array[45]), 13 (array[54]), 15 (array[63]) being loaded the first time, then those acceesses are all hits in future iterations

for set 2, every access is a miss and there 2 accesses per each of the 1000 loop iterations

so 2007 misses

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Consider a 2-way set associative cache with

and which uses 32-bit addresses (on a system that does not use virtual memory).

Question 4 (4 pt; mean 3.68) (see above)

Reading from which of the following addresses could cause the cache to replace a value it has stored that was originally obtained from address 0x1234? Select all that apply.

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Question 5 (4 pt; mean 3.52) (see above)

Suppose the cache is initially empty and the following accesses are performed in this order:

  • read 4 bytes from an address with tag 0x40, index 0x2, offset 0x0
  • write 4 bytes to an address with tag 0x40, index 0x2, offset 0x0
  • read 4 bytes to an address with tag 0x41, index 0x2, offset 0x0
  • read 4 bytes to an address with tag 0x42, index 0x2, offset 0x0
  • read 4 bytes to an address with tag 0x43, index 0x2, offset 0x0
  • write 2 bytes to an address with tag 0x30, index 0x1, offset 0x0

As a result of the above accesses, we would expect ____ bytes to be written to memory from the cache.

Answer:
Key: 16 + 2 = 18

the read of tag 0x42, index 0x2, offset 0x0 will evict the value with tag 0x40, index 0x2, offset 0x0, which is dirty, causing a 16 byte write

then the write of 2 bytes will bypass being stored in the cache as a result of the write-no-allocate policy

As this question was initially keyed only 18 was accepted. Later we also accepted 16 based on the reading that accesses that go to the cache and are then forwarded by the cache to memory are not "written to memory from the cache".

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Question 6 (4 pt; mean 3.1) (see above)

Suppose the cache is initially empty and the following accesses are performed in this order:

  • read 4 bytes from an address with tag 0x40, index 0x2, offset 0x4
  • read 4 bytes from an address with tag 0x40, index 0x2, offset 0x8
  • write 4 bytes to an address with tag 0x40, index 0x2, offset 0xc
  • read 4 bytes from an address with tag 0x41, index 0x2, offset 0x0
  • read 4 bytes from an address with tag 0x42, index 0x2, offset 0x0
  • write 4 bytes from an address with tag 0x41, index 0x2, offset 0x4
  • read 4 bytes from an address with tag 0x43, index 0x2, offset 0x8
  • write 4 bytes to an address with tag 0x44, index 0x2, offset 0xc

After these accesses run, which blocks associated which cache tags in set index 0x2 will have their dirty bits set? Write the tag values separated by commas. If no dirty bits will be set, write "none".

Answer:
Key: 0x41

reading a value with tag 0x42 evicts the value with tag 0x40 (LRU at that time); then reading a value with tag 0x43 evicts the value with tag 0x42 (LRU ta that time). The write to a value with tag 0x44 bypasses the cache entirely (write-no-allocate). As a result the cache set 0x2 will store tags 0x41 and 0x43. The value stored with tag 0x41 will be dirty, since it has been written since it was last removed from the cache.

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quiz for week 8

Suppose a system has:

Question 1 (4 pt; mean 3.77) (see above)

Each tag stored in the TLB takes up ____ bits.

Answer:
Key: 13

26 - 10 (page offset) - 3 (32/4 = 8 sets in TLB)

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Question 2 (3 pt; mean 2.86) (see above)

Assuming both accesses would be data cache hits and TLB hits, reading the byte from virtual address 0x12345 would ______ use the same TLB set as reading the byte from virtual address 0xF2345.

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Question 3 (3 pt; mean 2.87) (see above)

Assuming both accesses would be data cache hits and TLB hits, reading the byte from virtual address 0x12345 would ______ use the same TLB entry as reading the byte from virtual address 0xF2345.

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Question 4 (3 pt; mean 2.38) (see above)

Assuming both accesses would be data cache hits and TLB hits, reading the byte from virtual address 0x12345 would ______ use the same data cache set as reading the byte from virtual address 0xF2345.

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Consider the following code that uses the POSIX ("pthreads") API:

void *bar(void *x) {
    return NULL;
}
void *foo(void *x) {
    pthread_t p1, p2;
    pthread_create(&p1, NULL, bar, NULL);
    pthread_create(&p2, NULL, bar, NULL);
    pthread_join(p1, NULL);
    return NULL;
}

int main() {
    pthread_t p1, p2;
    pthread_create(&p1, NULL, foo, NULL);
    pthread_join(p1, NULL);
    pthread_create(&p2, NULL, foo, NULL);
    pthread_join(p2, NULL);
}
Question 5 (4 pt; mean 2.21) (see above)

When main() is run, what is the maximum number of threads, including the initial thread that runs main(), that can be running at the same time?

Answer:
Key: 5
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Question 6 (4 pt; mean 2.84) (see above)

When the above program runs, the variable p1 in main and the variable p1 in some call to foo will ____.

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quiz for week 9

Consider the following code that uses multiple threads using the POSIX ("pthreads") API.

struct item {
    int value;
    struct item *next;
};
struct item *head;

void *add_to_list(void *argument) {
    int *p;
    p = (int*) argument;
    struct item *new_item = malloc(sizeof(struct item));
    new_item->value = *p;
    new_item->next = head;
    head = new_item;
    return new_item->next;
}

int main() {
    struct item start;
    start.value = 0;
    start.next = NULL;
    head = &start;
    pthread_t p1, p2;
    int x = 1;
    void *new_ptr1; void *new_ptr2;
    if (0 != pthread_create(&p1, NULL, add_to_list, &x)) handle_error();
    if (0 != pthread_join(p1, &new_ptr1)) handle_error();
    x = 2;
    if (0 != pthread_create(&p2, NULL, add_to_list, &x)) handle_error();
    if (0 != pthread_join(p2, &new_ptr2)) handle_error();
    printf("%d %p %p\n", head->value, new_ptr1, new_ptr2);
}

Assume the calls to handle_error are never reached.

Question 1 (4 pt; mean 3.8) (see above)

The line new_item->value = *p assigns a value read from ___ to new_item->value.

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Question 2 (4 pt; mean 3.93) (see above)

The line new_item->value = *p assigns to a location on ____.

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Consider the following C code that uses the pthreads API and manages a linked list whose head is head:

struct item {
    int value;
    struct item *next;
    pthread_mutex_t lock;
};

struct item *head;
pthread_mutex_t head_lock;

void AddItemAtTail(struct item *item) {
    item->next = NULL;
    pthread_mutex_lock(&head_lock);
    if (head == NULL) {
        head = item;
        pthread_mutex_unlock(&head_lock);
    } else {
        pthread_mutex_lock(&head->lock);
        struct item *prev = head;
        pthread_mutex_unlock(&head_lock);
        while (prev->next != NULL) {  // (1)
            struct item *old_prev = prev;
            pthread_mutex_lock(&prev->next->lock);
            prev = prev->next;
            pthread_mutex_unlock(&old_prev->lock);
        }
        prev->next = item;
        pthread_mutex_unlock(&prev->lock);
    }
}

struct item *GetAndRemoveAtHead() {
    struct item *result = NULL;
    pthread_mutex_lock(&head_lock);
    if (head != NULL) {
        struct item *result = head;
        pthread_mutex_lock(&result->lock);   // (2)
        head = result->next;
        pthread_mutex_unlock(&result->lock); // (2)
    }
    pthread_mutex_unlock(&head_lock);
    return result;
}

Assume that all needed header files are included, and pthread_mutex_t options are initialized.

Question 3 (4 pt; mean 3.89) (see above)

If there are two simulatenous calls to AddItemAtTail, then under what circumstances can two different calls both be executing code within the while loop (and not waiting for a lock)? (Choose the most specific correct answer.)

  1. example: given list A, B, C, D, E; thread 1 can be executing struct item *old_prev = prev; for prev=C (holding C, just released B); thread 2 can b executing struct item *old_prev = prev; for prev=B *holding B, just released A)

  2. we accepted this on the basis of it being arguably "more specific" --- we should have written to choose the "least restrictive answer" or similar.

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Question 4 (4 pt; mean 3.4) (see above)

If the mutex lock and unlock labeled (2) were removed, then there'd be a potential for a race condition. Which of the following race conditions would be possible? Select all that apply.

  1. head_lock causes these calls to happen one at a time

  2. head_lock causes these calls to happen one at a time

  3. AddItemAtTail() chooses head as prev while GetAndRemoveAtHead has chosen head a result, then head = result->next sets head to NULL in Remove, then prev->next = item sets result->next to something, but that isn't going to be on the list

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Question 5 (4 pt; mean 3.98)

Suppose we modify the dining philosophers to put all chopsticks in the center of the table where each of the philosophers takes the first of those chopsticks that is available.

We can represent that using the following psuedocode:

    Lock chopsticks[NUM_CHOPSTICKS];

    int GetChopstick() {
        for (int i = 0; i < NUM_CHOPSTICKS; i++) {
           if (trylock(chopsticks[i]))
               return i;
           /* in version as posted: 
           else
               return -1;
            */
        }
        /* not version as posted: */ return -1; 
    }

    void PutDown(x) {
       Unlock(chopsticks[x]);
    }

    void Eat() {
        left = right = -1;

        while (left == -1)
            left = GetChopstick();

        while (right == -1)
            right = GetChopstick();

       // use chopsticks and eat

       PutDown(left)
       PutDown(right)
    }

In the above psuedocode:

For each of the following scenarios, is deadlock possible? Select all that apply.

in this question as originally asked, the psuedocode as buggy in having a return -1 in the loop instead of outside it, as shown in the correction above. With this, the pseudocode disagrees with the description"take the first chopstick available"

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quiz for week 10

Question 1 (8 pt; mean 7.74)

Consider the following psuedocode:

mutex_t mutex;
cond_t cv;
int locked[NUM_ACCOUNT] = {0, 0, 0, ... 0};

// assume withdraw() and deposit() do what the function names say
/*line 1*/ void transfer(acct1, acct2, amt) { // transfer amt from acct1 to acct2
/*line 2*/   mutex_lock(&mutex)
/*line 3*/   while (locked[acct1]) cv_wait(&cv, &mutex);
/*line 4*/   locked[acct1]=1;
/*line 5*/   while (locked[acct2]) cv_wait(&cv, &mutex);
/*line 6*/   locked[acct2]=1;
/*line 7*/   withdraw(amt, acct1);
/*line 8*/   deposit(amt, acct2);
/*line 9*/   locked[acct1]=0;
/*line 10*/  locked[acct2]=0;
/*line 11*/  mutex_release(&mutex);
/*line 12*/  signal(&cv);
/*line 13*/}

What is wrong, if anything, with this code? (If nothing is wrong, select no options below.)

  1. means locked is being manipulated without the lock held, so compiler/processor won't ensure updates to it and the accounts are ordered properly for other threads. (If we did something like add a new unlock after line 6 and add a new lock before line 9, that would be fine.)

  2. If there's any other code that manipulates locked, this is almost certainly true. (This seems likely since it would be rather sill yto have only a transfer() function using this account locking idea.) We probably hould have asked a version of this question where this code was restrucuted to release the lock before line 7 and reacquire it before line 9, which would be a good idea to allow for actual concurrency.

  3. accepted because of transfer(0, 0, ...) idea, though we don't think it's clear that's really a problem with this code (as opposed to the code calling it)

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Question 2 (5 pt; mean 4.4)

Consider the following potentially buggy code that is intended to allow multiple reader threads to be reading concurrently in a shared buffer and intended to ensure that a thread writing to the shared buffer must have exclusive access.

pthread_mutex_t lock;
pthread_cond_t proceed;
//initialization not shown

int reading = 0;
int writing = 0;

void reader(void) {
    pthread_mutex_lock(&lock);
    while (writing) pthread_cond_wait(&proceed, &lock);
    reading++;
    pthread_mutex_unlock(&lock);

   //reading code here

    pthread_mutex_lock(&lock);
    reading--;
    pthread_cond_signal(&proceed);
    pthread_mutex_unlock(&lock);
}

void writer(void) {
    pthread_mutex_lock(&lock);
    while (reading) pthread_cond_wait(&proceed, &lock);
    writing++;
    pthread_mutex_unlock(&lock);

   //writing code here

    pthread_mutex_lock(&lock);
    writing--;
    pthread_cond_signal(&proceed);
    pthread_mutex_unlock(&lock);
}

Assume that all appropriate header files are included and that code that accesses the shared buffer is included where //reading code here and //writing code here are.

Which of the following are bugs in this code or otherwise true about the code? Select all that apply.

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Question 3 (4 pt; mean 3.93)

Consider the following code:

int partial_mins[n];  //assume we initialize this to all MAX_INT in main()
int data[SIZE]; //filled with data for which we will find the min value
int chunk_size;
// SIZE and NUM_THREADS are defined elsewhere

void *find_min(void *raw_thread_num) {
  int thread_num = (int)raw_thread_num;
  int chunk_size = (SIZE / NUM_THREADS);
  for (int i = chunk_size * thread_num; i < chunk_size * (thread_num +1); i++) {
    if (data[i] < partial_mins[thread_num])
      partial_mins[i] = data[i]
  }
}

This function can be run by multiple instances of pthread_create to obtain a "partial minimum" of a subset of the shared array data. Later, other code can take the minimum of these minimums to find the overall minimum of the array. Which variables are likely to exhibit false sharing when the code is run? Select all that apply.

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Question 4 (4 pt; mean 2.49)

Suppose we use a scheme with acknowledgments and sequence numbers like described in lecture to send data from machine A to machine B over a network that follows the mailbox model.

In this scheme, machine A does not send a data message until after it receives an acknowledgment message for its previous data message, so that it can handle cases where the network fails to deliver its data network.

Suppose while a particular data transfer occurs, the network is reliable for sending messages from A to B, but very unreliable for sending messages from B to A. So, all the messages from A to B are received correctly and not delayed, but every third message (starting with the third one) from B to A is lost.

If the data transfer sends data from A to B that is split across 1000 data messages, how many messages, including lost acknowledgment messages, will be sent across the network in total?

Answer:
Key: 2998

A will send 0, then 1, then miss ACK for 2, resend 2, then send 3, then miss ACK for 4, then resend 4, send 5, miss ACK for 6, and so on.

So A ends up resending 2, 4, 6, 8, ..., 998 = 499 messages

B sends an acknowledgment for each of A's 1499 messages

1499 * 2 = 2998

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Question 5 (4 pt; mean 3.88)

Suppose we have a network of networks setup as follows:

Router B's routing table will have an entry that corresponds to the IP address for machine D which indicates to send packets addressed to machine D to ______.

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quiz for week 11

Suppose we are doing network address translation and have the following table:

remote address:portpublic IP portprivate IP addressprivate IP port
1.2.3.4:44359423192.168.1.464342
2.3.4.5:2359424192.168.1.313232

Assume this is on a router with an IP address of 11.12.13.14 on the public network and 192.168.1.1 on a private network. Network address translation allows all the machines on the private network to share the router's public IP address.

Question 1 (4 pt; mean 3.81) (see above)

Based on the above table, if a packet comes in with a source address of 1.2.3.4, source port of 443, and destination address of 11.12.13.14, and destination port of 59423, the router should send _____.

  1. packet should have source address of 1.2.3.4, source port of 443, destination of address of 196.168.1.4, destination port of 64342

Something we kind-of covered by mentioning how the mapping between addresses and sockets is tracked and how routing works, but not as explicitly as I [Reiss] thought when originally writing this question is that IP packets generally contain the original source address and the final destination address. In retrospect, I should have only asked about the final destination address given our lack of detailed coverage.

If there were no network address translation, then we'd preserve the original source address and the destination address would already be the final address of the final machine. With network address translation, the destination address is "wrong", it should be the final machine, but the source address is already correct. The final machine initiaited the connection using its private IP address+port and the remote IP address+port, so it needs to continue seeing those addresses throughout the connection.

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Consider the following protocol for an forum system:

Question 2 (3 pt; mean 2.84) (see above)

Which of the following can a passive eavesdropper do? Select all that apply.

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Question 3 (8 pt; mean 5.71) (see above)

Which of the following can an active machine-in-the-middle attacker potentially do? Select all that apply.

  1. encrypted but not authenticated. Since our assumption in this class is that encryption, unless otherwise stated, is not authenticated, the attacker can change the encrypted message containing this. At a minimum, they can make the contents become junk. Although a message authentication code is used, it's not computed using anything about the post contents, so the manipulation will not be detected.

  2. same reasonining as changing the contents

  3. if the encryption uses some scheme that's malleable via something like bit-flipping, then the manipulation could be targetted this precisely

  4. requires constructing the MAC of the username and "forum post success", which is not possible without the shared key

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Question 4 (4 pt; mean 3.77) (see above)

If we wanted to change the symmetric encryption used for messages when retreiving all posts from a forum to use public-key encryption, then, the corresponding private key would be ____.

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quiz for week 12

Consider the following protocol for a forum system (which is similar to the last quiz, but has some more message authentication codes):

Question 1 (4 pt; mean 3.81) (see above)

Suppose a user makes a request to send a message to forum A, then to send another message to forum A, then to send a message to forum B, and these are the only requests they have made to the server. An active machine-in-the-middle attacker could potentially do which of the following? Select all that apply.

  1. meant to write "same text they intended to post to forum B", but did not. Without that change, this is just replaying the first or second post. With that change would be prevented by second MAC user sends.

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Question 2 (4 pt; mean 3.77) (see above)

Suppose a user makes a request to read all messages in forum A, then to read all messages in forum B, then to read all messages in forum A again, and these are the only requests they have made to the server. An active machine-in-the-middle attacker could potentially do which of the following without the user's client having the information to detect that its communications were tampered with? Select all that apply.

  1. was originally miskeyed. To do this with only editing the server's messages would require forging the MAC. But we can edit the forum the client requests to an empty one (assuming there is an empty one), since I neglected to make that be covered by a MAC.

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Question 3 (5 pt; mean 4.62)

Consider a communication scenario with participants A, B, C, an active "machine-in-the-middle" attacker M, and an eavesdropper E.

In advance, the following sets of symmetric keys are shared as follows:

(Assume that symmetric key shared are only available to those who it is shared with.)

Suppose A sends a sequence of text lines to both B and C, by doing the following for each line of text:

Given this scheme, which of the following are likely possible?

  1. true if C can somehow stop B from receiving a legitimate message from A and replace it with their own (like if C were cooperating with M); not quite true otherwise. I should have specified more explicitly our assumptions about whether C was in a privileged network position.

  2. can't forge A/C message authentication with correct counter value

  3. encryption algorithm would not provide confidentiality if this is the case

  4. better question would have been about B detecting it, but answer the same either way

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Question 4 (4 pt; mean 3.81)

Consider a TLS handshake like the one we described in lecture. Suppose a client contacts a server which has a different name than the name of the server it expected to connect to. Then the connection would most likely fail because ___.

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Suppose a single-cycle processor takes 100 milliseconds to execute a program with 100 million instructions.

We modify the single-cycle processor into a five-staged pipelined processor using a design like we discusssed in lecture and using pipeline registers that have a pipeline delay of 20 ps.

Question 5 (4 pt; mean 3.39) (see above)

If there were no data or control hazards in the program on the pipelined processor and we split the work for instructions perfectly among the pipeline stages, the pipelined processor would take around _____ milliseconds to execute the program. Round your answer to the nearest integer number of milliseconds.

Answer:
Key: 22

original cycle time is 1000 ps, if we don't assume we reuse existing registers as pipelien registers, new cycle time is about 1000 ps / 5 + 20 = 220 ps, yielding 22.0 ms

if we assume that we reuse some existing registers that are binding in the 1000 ps cycle time, then maybe we only have 980 ps of work to divide, yielding 980 / 5 + 20 = 216 ps, yielding 21.6 ms

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Question 6 (8 pt; mean 7.17)

Consider the following assembly code:

subq %r9, %r8
xorq %rdx, %r9
imulq %r9, (%r13)
addq %r8, %r13
movq (%r9), %r11
orq %r11, %r12

If we had a processor with the following pipeline stages (following the names used in lecture):

Then which of the following things in the code example are data hazards when the code is run on the pipelined processor?

  1. assuming no stalling/other hazard resolution (which we do in general to see if a hazard exists), when addq is in decode, imulq is in execute/memory, xorq is in writeback, and the subq has completed entirely. The addq will read the corret value "for free". This situation only gets better if stalling is needed because of the other instructions.

  2. read/write happen in correct order in pipeline naturally

  3. movq in decode, addq in execute/memory, imulq in writeback, the xorq has completed entirely. So the movq will read the correct value without any forwarding/stalling.

  4. reads are independent of each other

  5. the imulq does not modify %r13 (the value in the register %r13 and the value in memory at the address formed using %r13 are different values), so there's no concern with addq reading the wrong value of %r13. addq's modification of %r13 won't be a problem since imulq's read o fthe register %r13 will happen before the addq writes anything.

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quiz for week 13

Question 1 (4 pt; mean 3.78)

Suppose a 5-stage pipelined processor, similar to the design discussed in lecture, executes a program with 100 million instructions.

If there were no hazards, this program would execute in about 100 million cycles.

Suppose there are not data hazards in the program on the pipelined processor, but there are control hazards in the form of conditional jumps.

Assume that when a conditional jump is mispredicted, incorrect instructions are fetched during the decode and execute stages of the conditional jump and the correct next instruction is fetched during the jump's memory stage. (By "correct next instruction", we mean the target of the jump (the address specified by its operand) if it is taken, or the instruction that follows it in memory if it is not.) When a jump is predicted correctly, the correct next destination of the jump fetched during its decode stage (and no incorrect instructions are fetched).

If 5% of the instructions are conditional jumps, and the processor can predict them with 80% accuracy, then we'd expect the program to execute around __% slower than if we predicted the jumps perfectly.

Answer:
Key: 2
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Consider the following assembly snippet:

movq %r9, (%r10)
addq %r10, %r11
movq (%r11), %r10
subq %r10, %r9
Question 2 (4 pt; mean 2.81) (see above)

Suppose we execute the above code on a six-stage pipelined processor with the following pipeline stages:

  • fetch
  • decode
  • execute
  • memory part 1
  • memory part 2
  • writeback

Assume the two part memory stages use the same inputs and outputs as an unsplit memory stage, and they need the inputs (the address to access and any value to store) near the beginning of the memory part 1 stage and only have outputs (any value loaded) near the end of the memory part 2 stage.

If the movq %r9, (%r10) finishes its writeback stage during cycle number 0, then the subq %r10, %r9 should finish its writeback stage during cycle number ____.

Answer:
Key: 5

<

pre> x x x x x 0 1 2 3 4 5 /pre>

movq F  D  E M1 M2 W
addq    F  D  E M1 M2 W
movq       F  D  E M1 M2 W
subq          F  D D  D  E M1 M2 W
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Question 3 (6 pt; mean 5.56) (see above)

If we execute the above code on an out-of-order processor that uses register renaming, then we would expect movq (%r11), %r10 to read from one of the physical registers that ____. Select all that apply

  1. was originally miskeyed

  2. was originally miskeyed

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Question 4 (4 pt; mean 3.33)

Consider the following assembly snippet:

movq (%r8), %r9
addq %r9, %r10
subq %r10, %r11
imulq %r10, %r12
movq %r12, (%r9)

On an out-of-order processor with sufficiently many functional units, the instruction subq %r10, %r11 in the above assembly snippet could be potentially be issued in the same cycle as ___. Select all that apply.

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Question 5 (4 pt; mean 2.96)

Consider the following loop:

begin:
    movq (%r8), %r9
    addq $512, %r8
    cmp %r9, %r10
    jmp begin

On an out-of-order processor with sufficiently many functional units, movq (%r8), %r9 could potentially be executing (reading a value from the data cache) ____. Select all that apply.

  1. needs %r9 from this iteration

  2. we can compute the next iteration's version of %r8 without getting %r9. Then, we can complete the movq for the next iteration and start the comparison --- all while the earlier movq is pending. This is probably likely if the earlier movq misses in the cache but the later one does not

  3. can compute both versions of %r8 without completing any memory accesses. if we have faster ALUs than data caches, it's rather likely that the arithmetic to compute %r8 for all the iterations will complete before we can start all the data cache accesses

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Suppose an out-of-order processor has two execution units for arithmetic, each pipelined with four stages. All arithmetic instructions use all four stages.

Question 6 (4 pt; mean 2.89) (see above)

How many cycles minimum would this processor need to do the arithmetic for the following assembly snippet? (Don't include time needed for instruction fetch, register renaming, etc.)

imulq %r8, %r9
imulq %r8, %r10
addq %r11, %r8
addq %r9, %r8
xorq %r10, %r8
Answer:
Key: 12

was initially miskeyed due to an editing mistake (meant not to have all the last 3 instructions use %r8); sorry for the error

example: cycle 1: imul1, add1 start; cycle 2: imul2 starts; cycle 4: imul1, add1 finish; cycle 5: imul2 finishes, add2 starts; cycle 8: add2 finishes, cycle 9: xor starts; cycle 12: xor finishes

also accepted 13

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quiz for week 14

Question 1 (4 pt; mean 3.09)

Consider the following C snippet

int i = 0; 
do {
    i += 1;
    if (i % 2 == 0) {
        A();
    } else {
        B();
    }
} while (i != 100);

Assume the above code is compiled such that there is one conditional jump implementing the if statement and one condtiional jump implementing the do-while loop condition.

Suppose we use a branch predictor with a lookup table that identifies for each instruction whether it was taken the last time it ran.

Rounded to the nearest percent, we would expect a branch predictor accuracy of ___% if the above code is run repeatedly. Round your answer to the nearest integer number of precent.

Answer:
Key: 49

i != 100 mispredicted for i = 1, i = 100 (correct 98 out of 100 times); i % 2 mispredicted every time (100 out of 100 times)

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Consider the following C code:

const char *hidden_string;

bool TextInString(const char *part) {
    int length_hidden = strlen(hidden_string);
    int length_part = strlen(part)
    for (int i = 0; i < length_hidden - length_part; i += 1) {
        bool match = true;
        for (int j = 0; j < length_part; j += 1) {
            if (hidden_string[i+j] != part[j]) {
                match = false;
                break;
            }
        }
        if (match)
            return true;
    }
    return false;
}

For the following questions, assume the code is compiled in a way which does not omit any comparison operations above or run multiple comparisons in parallel. Also assume that the time required for each instruction (comparision, memory access, etc.) is consistent. (For example, variations because of values sometimes not being in cache are not significant.)

Question 2 (4 pt; mean 3.75) (see above)

Suppose:

  • hidden_string is 6 characters long
  • hidden_string only contains "a"s and "b"s and "c"s,
  • the following are timings and results for calls to TextInString:
    input time return value
    "a" 10 true
    "b" 15 true
    "c" 18 true
    "aa" 15 true
    "ab" 21 true
    "ac" 25 false
    "ba" 26 false
    "bb" 18 true
    "bc" 26 true
    "cc" 28 true

Based on this information, what is the best guess about the value of hidden_string?

Answer:
Key: aabbcc
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Question 3 (4 pt; mean 3.48)

Consider the following C code:

unsigned char array[10000];
...
array[200] += 10

If this is run on a system where: * array is located at address 0x100400 * chars are 1 byte * virtual memory is not enabled * there is a 131072 byte (2 to the 17th power byte) 2-way data cache with 128-byte blocks

Then the running the C code might evict a value from what set index in the data cache?

Answer:
Key: 9

(0x100400 + 200)/128 = 0x2009, cache has 0x200 sets, so set 0x9

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Consider the following code:

unsigned char check_array[32768];
int mystery = /* unknown */;

int Check(int key) {
    return check_array[(key + mystery) % 32768];
}

Suppose that:

Question 4 (4 pt; mean 2.91) (see above)

Suppose we determine that calling Check evicts from the data cache sets as follows:

key value | evicts values from cache set indexes
------------------------------------------------
0         | 15, 72, 435
32        | 15, 72, 435
48        | 15, 72, 436
128       | 15, 72, 437
8240      | 15, 52, 72

Based on this information what is a possible value for mystery?

Answer:
Key: a value between 27856 and 27871 +/- any multiple of 32768

originally we erroneously wrote % 16384 instead of % 32768, and 4096 instead of 8240 for the last value

(0 + mystery) // 64 +/- multiple of 512 (number of cache sets) = 435

(32 + mystery) // 64 +/- multiple of 512 (number of cache sets) = 435

(48 + mystery) // 64 +/- multiple of 512 (number of cache sets) = 436

...

let's choose the mulitple of 512 to be 0 for simplicity, for now

mystery // 64 = 435 implies mystery in [435 * 64 = 27840, 27840 + 63 = 27903]

(32 + mystery) // 64 = 435 implies mystery in [435 * 64 - 32 = 27808, 27808 + 63 = 27871]

(48 + mystery) // 64 = 436 implies mystery in [436 * 64 - 48 = 27856, 27856 + 63 = 27919]

overlap here implies mystery in [27856, 27871]

the multiple of 512 offsets this by 512 * 64 = 32768

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Question 5 (4 pt; mean 0.24)

Consider the following C code:

struct Files all_files[NUM_FILES];
int GetLastByteOfFile(int index) {
    if (index >= 0 && index < all_files) {
        struct File *file = &all_files[index];
        if (file->type == MEMORY) {
            return file->data[file->size - 1];
        } else if (file->type == DISK) {
            return GetLastByteOfDiskFile(file)
        } else {
            return -1;
        }
    } else {
        return -1;
    }
}

If the above function runs in kernel mode, we might be able to use a Spectre-style attack where the cache evictions caused by memory access of file->data[file.size - 1] allows us learn about the value of an arbitrary memory location. To perform this attack, the attacker would prefer to choose an out-of-bounds index such that ___.

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