> Return to course pageReturn to index

Final

You may use any resource that existed prior to this exam opening, including websites, books, etc; but should not consult friends, tutors, forums, or other interactive help for this exam.

You must not share any information about this exam (even how you felt about it) with any party (even others who have taken it) until after it closes at 2020-05-07 23:59 EDT.

The following ask about adding limitations to computer functionality.

Question 1 (dropped) (see above)

Suppose we want to limit the use of the xorq command to only certain users or operation modes. This would require modification of

Question 2 (see above)

Suppose we want to limit all user-mode programs so they can only access to files have an even number of letters in their names. This would require modification of

Question 3 (see above)

Suppose we want to throttle bandwidth so each user could only send 1MB of network traffic per minute. This would require modification of

The following ask about interrupts and related concepts

Question 4 (see above)

What's the difference between an interrupt number and a system call number?

Question 5 (see above)

The following are all true of interrupts; which are also true of signals?

We have often noted each of the following things about memory this semester; these questions ask how they have been refined by our understanding of virtual memory

Question 6 (see above)

Linux on x86-64 splits memory in half: the lower half is user-mode and the upper half is kernel-mode

Question 7 (see above)

The call stack (the one handled by pushq, callq, etc) grows toward smaller addresses

Question 8 (dropped) (see above)

When a process is suspended, allowing other processes to use the processor, its memory is inaccessibly.

Consider the 4-level page table hierarchy we discussed Intel processors using, with a 4K pages, 48-bit virtual addresses, and 52-bit physical addresses

Question 9 (see above)

If I run movq (%rax), %rbx when (%rax) is on a page that is not in the TLB, how many memory accesses does the instruction perform? Answer as a base-10 integer, like "1" or "39"

Answer:
Question 10 (see above)

If I run movq (%rax), %rbx when (%rax) is on a page that is in the TLB, how many memory accesses does the instruction perform? Answer as a base-10 integer, like "1" or "39"

Answer:
Question 11 (see above)

If my code accesses the 50-bit address 0x2100010001000

Question 12

If a disk read is performed via Direct Memory Access (DMA),

The following ask about the ability of devices on a bus to interact. In particular, assume that a bus-topology network connects the keyboard, disk, network card, and processor.

Assume that any special status a bus-connected component can have (hub position, master status, etc) is held by the processor and not the other components.

Question 13 (see above)

Suppose I create a nefarious disk that is programmed to log every keystroke you make. Assume I put any computing power needed for this task inside the disk hardware.

Question 14 (dropped) (see above)

Suppose I create a nefarious disk that is programmed to send your files to me over your Internet connection. Assume I put any computing power needed for this task inside the disk hardware, but do not have network connectivity in the disk itself.

HTTPS delivered web requests and replies using TLS, TCP, and IP. The TLS encrypts the request and reply body, but does not encrypt the IP and TCP headers.

Question 15 (see above)

Why does TLS not encrypt the IP header?

Question 16 (see above)

Why does TLS not encrypt the TCP header?

The following ask about digital signatures

Question 17 (see above)

Which of the following is used to sign a document?

Question 18 (see above)

Which of the following is used to verify the signature of a document?

Question 19 (see above)

A digital certificate is

The following ask about caches, in particular the memory cache hierarchy

Question 20 (see above)

Why do caches have larger blocks that a single access will need?

Question 21 (see above)

Why do caches have multiple lines per set?

Question 22 (see above)

Why do caches have multiple small sets instead of one large one?

Question 23 (0.5 points) (see above)

Why are some caches write-back?

Question 24 (0.5 points) (see above)

Why are some caches write-through?

Question 25

Which of the following best describes Amdahl's Law?

Question 26

Which two of the following correctly describe concurrency and parallelism?

Question 27

Which of the following are true of synchronization primitives?

Most synchronization primitives can be created using several other primitives and a few auxiliary data structures. Which of the following is closest to implementing barriers with other pthreads primitives?

Question 28 (see above)

The pthread_barrier_t needs a condition variable for threads to wait on, a mutex to lock access to other variables, and which of the following?

Question 29 (see above)

If our pthread_barrier_t was implemented as

lock the mutex
manipulate variables
if (variables suggest should wait) {
    wait on condition variable
} else {
    release all waiting threads
}
unlock the mutex

what would go wrong? Assume the barrier requires at least two threads to continue.

Question 30 (see above)

If our pthread_barrier_t was implemented as

lock the mutex
manipulate variables
if (variables suggest should wait) {
    unlock the mutex
    wait on condition variable
} else {
    unlock the mutex
    release all waiting threads
}

what would go wrong? Assume the barrier requires at least two threads to continue.

The following ask about Dining Philosophers and its solutions documented in Lab 09.

Question 31 (see above)

The "arbitrator" solution to dining philosophers ensures there is no deadlock by removing which of the necessary conditions of deadlock?

Question 32 (see above)

The "resource hirearchy" solution to dining philosophers ensures there is no deadlock by removing which of the necessary conditions of deadlock?

Question 33

Pipelining ____ throughput and ____ latency.

Question 34

Out of order execution ____ throughput and ____ latency.

Question 35

Speculative execution can increase the performance of

Both Spectre and Meltdown exploits included (a compiled or language-specifc version of) the code

y = arr[(*x) * 4096]

where x was a pointer to an address that should not be accessible, but whose value was leaked by the exploit; arr was a pointer to memory owned by the attacker; and y was a register owned by the attacker.

Question 36 (see above)

After running the above code, how do these exploits learn the contents of *x?

Question 37 (see above)

Why the 4096 multiplicand?

Return to course pageReturn to index normal