This is a small homework to expose you to the hclrs tool we’ll use for the next several labs and homeworks.

1 Write irrr.hcl

To start exploring HCL, create a simulator that handles nop, halt, irmovq, rrmovq, and unconditional jmp.

Create a file called irrr.hcl to create this simulator.

We suggest implementing the instructions in the order listed above, adding functionality as needed:

1.1 Implement nop/halt

1. Have a register for the program counter like in the first HCL lab. You may start with the code you implemented for the lab.
2. Extract the icode from each instruction.
3. Set Stat. It should be STAT_HLT if the icode is halt, STAT_INS for an icode not in Y86 (e.g., > 0xb), STAT_AOK otherwise.

1.1.1 Test cases

If you run your simulator on y86/halt.yo, and it should halt after one cycle, and if you run it on y86/nophalt.yo, it should halt after 4 cycles.

1.2 Implement irmovq

4. Fetch and split each the rest of each instruction. Start by extracting the rB and valC fields for IRMOVQ.
5. If the instruction is an IRMOVQ, send valC to the register file as the new value for register number rB. If the instruction is not an IRMOVQ or RRMOVQ, do not write to the register file (specify a destination register of REG_NONE).

1.2.1 Test cases

If you run your simulator with the -q flag on y86/irmovq.yo, you should see

+----------------------- halted in state: ------------------------------+
| RAX:              222   RCX:                2   RDX:               22 |
| RBX:                0   RSP:                0   RBP:                0 |
| RSI:                0   RDI:                0   R8:                 0 |
| R9:                 0   R10:                0   R11:                0 |
| R12:                0   R13:                0   R14: fedcba9876543210 |
| register pP(N) { pc=0000000000000033 }                                |
| used memory:   _0 _1 _2 _3  _4 _5 _6 _7   _8 _9 _a _b  _c _d _e _f    |
|  0x0000000_:   30 f0 01 00  00 00 00 00   00 00 30 f1  02 00 00 00    |
|  0x0000001_:   00 00 00 00  30 f2 22 00   00 00 00 00  00 00 30 f0    |
|  0x0000002_:   22 02 00 00  00 00 00 00   30 fe 10 32  54 76 98 ba    |
|  0x0000003_:   dc fe                                                  |
+--------------------- (end of halted state) ---------------------------+
Cycles run: 6

If you see 0 in RAX instead of 222 it is likely that you’re writing to the register file for halt as well as irmovq.

1.3 Implement rrmovq

6. Split the rA field from the instruction for RRMOVQ.
7. If the instruction is an RRMOVQ, send rA to the register value so you can get the value of the register. Send this value to the register file as the new value for register number rB. You will need a MUX for the register file input signal.

1.3.1 Test cases

The test case in y86/rrmovq.yo:

irmovq $5678, %rax
irmovq $34, %rcx
rrmovq %rax, %rdx
rrmovq %rcx, %rax
 

should result in registers ending in the following state:

| RAX:               22   RCX:               22   RDX:             162e |

In addition, your simulator should agree with tools/yis on y86/prog8.yo

1.4 Implement unconditional jmp

Note that the for jXX the immediate value is in bits [8, 72) not [16, 80). You’ll thus need a mux for valC.

You’ll add conditional handling to jXX as part of the next homework, but not part of this homework.

8. Add a MUX for valC to extract the immediate value correctly for jmp instructions (or, alternately, use a wire with a different name for valC for jmp instructions).
9. Add a MUX for the PC register value to select valC if the icode is JXX.

1.4.1 Test cases

If you run your simulator on y86/jmp.yo, which is an assembled version of

    irmovq 0xbad, %rax
    jmp A
    irmovq 0xbad, %rbx
    halt
A:
    irmovq 0xace, %rax
    halt
     

you should end up with ace, not bad, in rax and nothing in rbx.

There is a trace of the expected cycle-by-cycle output in testdata/seq-traces/jmp.txt.

2 Overall testing

In addition to testing individual files manually with ./hclrs irrr.hcl file.yo, you can run make test-irrr to test your irrr.hcl. This will compare it to outputs which are supplied with HCLRS in the testdata/seq-reference directory over the list of .yo files in testdata/irrr-tests.txt. The behavior of your processor should over these files should be identical to the final single-cycle processor you will make in a later lab and to tools/yis run on the .yo file.

(If you want to save the output from this make test-irrr to a file, you can use something like make test-irrr >test-irrr-output.txt 2>&1 (the 2>&1 says to also save error output, not just normal output).)

You can find traces of the expected cycle-by-cycle output of all tests in testdata/seq-traces, which may help in debugging test failures.

3 Submit

Submit a file named irrr.hcl on the submission page.