for conflicts1.png:
- simpler example to talk about data cache miss measurement
    - assuming a 32B direct-mapped cache w/2B blocks
        - 5 set index + block offset bits
    - access pattern: 0x00, 0x10, 0x20, ..., 0xF0, 0x00, 0x10, 0x20, ...
        - C code is loop with that pattern (if array at address 0)
    - set index + block offset bits of pattern:
                00000 (for 0x00), 10000 (for 0x10), 00000 (for 0x20), 10000, ....
        - accesses only use sets 0 and 7 of 16-set cache
    - multiple of 32B apart (= 2^(set index + block offset bits)) 
        <-> same set index + block offset bits <-> conflict in cache
    - first access to array[0] in second loop (0x00)
        conflicts with access to array[14*16] in first loop (0xE0)
        so must be miss

for conflicts2.png:
- this is for the post-quiz question with a direct-mapped cache
    - because it's a 64KB direct mapped cache, values 64KB apart in the array map to the same set
    - array[0] (beggining of array + 0) and array[8*1024] and array[16*1024] and ... map to set 0
    - array[1024] (beggining of array + 0) and array[9*1024] and array[17*1024] and ... map to the same set



for conflicts3.png:
- this is for the post-quiz question with a set-associative cache
    - each way of the cache is 0.5MB
    - alternately: 0.5MB = 2^(set index + block offset bits) bytes
    - array elements 0.5MB apart map to the same set
    - there are 8 array elements in each set that is used, but only 3 blocks to use
    - when accessing array[0] the second time, we've accessed 7 other values from same set
        - since LRU replacement: evicted