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Pre-quiz on fifth week's material.

Question 1: The book has a single wire named valE. HCL2D splits it into which of the following?
Select all that apply

  1. reg_inputE

  2. reg_dstE

  3. mem_input

  4. mem_output

  5. mem_addr

Question 2: The book has a single wire named valM. HCL2D splits it into which of the following?
Select all that apply

  1. reg_inputM

  2. reg_dstM

  3. mem_input

  4. mem_output

  5. mem_addr

Question 3: Suppose the instruction memory returned an addq instruction. Where would we find rA?

  1. i10bytes[0..4]

  2. i10bytes[4..8]

  3. i10bytes[8..12]

  4. i10bytes[12..16]

Question 4: Suppose that you are debugging your processor and discover that bytes 0 through 7 of memory are being changed and should not be changed. Which of the following could cause this bug?
Select all that apply

  1. mem_writebit is 1 when it should be 0

  2. mem_addr is 0 when it should be something else

  3. mem_input has the wrong value

  4. mem_output has the wrong value

  5. reg_inputM has the wrong value

  6. reg_dstM has the wrong value

Question 5: Which of the following are illegal in HCL2D?
Select all that apply

  1. i10bytes = 3;

  2. reg_srcA = 3;

  3. wire t:2; t = 0b0011;

  4. reg_inputE = reg_outputA; reg_inputM = reg_outputA;

  5. reg_inputE = reg_outputA; reg_inputE = reg_outputB;

Question 6: The following is legal HCL2D code:

wire a:8, b:8;
a = b;
b = 7;

When it is run, what will be the value of a?

  1. 8

  2. 7

  3. 0

  4. undefined

  5. 'b'

  6. nothing at first; it will get a value on the second clock cycle

  7. none of the above

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