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This quiz selects topics from across 4.5; some questions refer to particular sections, which should be the same in the 2nd and 3rd editions.

There is an aside in section 4.5.3 about m_stat vs M_stat, ending with the phrase Understanding this naming convention is critical to understanding the operation of our pipelined processor.

Question 1 (0 points): (see above) Suppose that during the execute phase we are computing a value based on two other values. Which of the following sets of values would indicate we are doing something wrong?
Select all that apply

  1. Using e_corge and E_gralpy

  2. Using e_corge and e_gralpy

  3. Using E_corge and E_gralpy

  4. Using d_corge and d_gralpy

  5. Using D_corge and D_gralpy

Question 2 (0 points): (see above) It is always the case that if the book mentions a wire named

  1. E_corge then there is also a wire named e_corge

  2. E_corge then there is also a wire named d_corge

  3. E_corge then there is also a wire named m_corge

  4. e_corge then there is also a wire named E_corge

  5. e_corge then there is also a wire named D_corge

  6. e_corge then there is also a wire named M_corge

Question 3: Consider the following pipeline diagram

1 2 3 4 5 6 7 8
addq %rax,%rbx F D E M W
xorq %rcx,%rdx F D E M W
subq %rsi,%rdi F D E M W
andq %rsp,%rbp F D E M W

When subq is in the execute stage, what is in the memory stage?

  1. addq

  2. xorq

  3. subq

  4. andq

  5. none of the above

Question 4: Consider the following incomplete pipeline diagram, including some stalling due to a data dependency between addq and xorq

1 2 3 4 5 6 7 8 9
addq %rax,%rbx F D E M W
xorq %rbx,%rcx F D D D D E M W
subq %rsi,%rdi F

Given that subq was in fetch during cycle 3 and that it has no dependency on the preceding instructions, during what cycle would subq be in the memory stage? Answer as a normal base-10 number.

Answer:
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