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Question 1: When the outcome of a branch is guessed incorrectly in our book's pipelined Y86 processor, the branch takes ______ cycles to execute than on a pipelined processor without branch prediction.

  1. more cycles

  2. the same number of cycles

  3. fewer cycles

Consider the following assembly program, executed on our book's pipelined processor with branch prediction:

        subq %r8, %r8 /* set r8 to 0 */
        jg unreachable /* never taken */
        jmp next
next:   call empty
        halt

empty:  ret

Question 2: (see above) When the jg unreachable instruction is fetched, the previous subq %r8, %r8 instruction will be in what phase:

  1. fetch

  2. decode

  3. execute

  4. memory

  5. writeback

  6. not in the pipeline

Question 3: (see above) When the jmp next instruction is fetched, the previous jg unreachable instruction will be in what phase:

  1. fetch

  2. decode

  3. execute

  4. memory

  5. writeback

  6. not in the pipeline

Question 4: (see above) When the halt instruction is fetched, the previous call empty instruction will be in what phase:

  1. fetch

  2. decode

  3. execute

  4. memory

  5. writeback

  6. not in pipeline

Question 5: (see above) Which of these instructions will require a stall?
Select all that apply

  1. subq %r8, %r8

  2. jmp next

  3. call empty

  4. ret

Question 6: Consider the following assembly snippet:

addq %rax, %rbx  
nop
nop
nop
xorq %r8, %rbx

Do the andq and xorq instructions exercise a data hazard? If so, can the hazard be handled without stalling using forwarding?

  1. there is no hazard

  2. there is a hazard, but it can be handled with forwarding

  3. there is a hazard, and handling it will require stalling

Question 7: Consider the following assembly snippet:

addq %rax, %rbx  
nop
xorq %r8, %rbx

Do the andq and xorq instructions exercise a data hazard? If so, can the hazard be handled without stalling using forwarding?

  1. there is no hazard

  2. there is a hazard, but it can be handled with forwarding

  3. there is a hazard, and handling it will require stalling

Consider the following sequence of instructions:

addq %rax, %rbx
xorq %r8, %rbx

To handle the data hazard exercised by these instructions, we can implement forwarding from the ALU output to valB pipeline register after the decode stage.

Question 8: (see above) How many cycles does this forwarding path save versus stalling?

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. 5

Question 9: (see above) Which of the following values from pipeline registers does the logic for deciding whether to use this forwarding path need?
Select all that apply

  1. icode for addq

  2. icode for xor

  3. ifunc for addq

  4. ifunc for xor

  5. rA for addq

  6. rB for addq

  7. rA for xorq

  8. rB for xorq

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