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Question 1: Suppose we have 64KB pages, 8B page table entries, and a 2-level page table hierarchy. How many bits long is the usable virtual address (the VPNs and VPO combined)?

Answer as a normal base-10 number.

Answer:

Question 2: Memory permission bits (such as "read-only") are stored in
Select all that apply

page table entries
data pages
the TLB
operating system data structures

Question 3: The Linux operating system data structure vm_area_struct refers to a range of addresses. These ranges are usually aligned with page boundaries because

vm_area_structs store only physical page numbers, not whole addresses, to save space
vm_area_structs store only virtual page numbers, not whole addresses, to save space
the MMU reads the vm_area_struct and expects page boundaries
the OS uses the vm_area_struct to initialize page table entries so sub-page resolution is not useful
speed: alignment with page boundaries makes memory accesses faster

Question 4: The TLB is a cache, which means it splits its input into parts. Which of the parts used by data caches is missing, and why?

There is no tag because all the input bits are used for other purposes
There is no tag because there is nothing to compare them to
There is no index because the TLB is direct-mapped
There is no index because the TLB is fully associative
There is no offset because there is only one element per block
There is no offset because the TLB stores PPNs or PTEs, not bytes

Question 5: In the processor described in the textbook, the TLB lookup and L1 cache lookup can run partly in parallel. This is parallelism is possible because of careful selection of which of the following?
Select all that apply