+------------------- between cycles 0 and 1 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x0; loaded [30 f4 00 01 00 00 00 00 00 00 : irmovq $0x100, %rsp] +------------------- between cycles 1 and 2 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0xa; loaded [80 15 00 00 00 00 00 00 00 : call 0x15] +------------------- between cycles 2 and 3 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x15; loaded [00 : halt] +------------------- between cycles 3 and 4 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x15; loaded [00 : halt] +------------------- between cycles 4 and 5 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 0 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x15; loaded [00 : halt] wrote reg_inputE (0x100) to register reg_dstE (4, which is %rsp) because mem_writebit was 1, set memory at mem_addr (0xf8) to mem_input (0x13) +------------------- between cycles 5 and 6 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: 100 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x15; loaded [00 : halt] wrote reg_inputE (0xf8) to register reg_dstE (4, which is %rsp) +------------------- between cycles 6 and 7 ----------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: f8 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +-----------------------------------------------------------------------+ pc = 0x15; loaded [00 : halt] +----------------------- halted in state: ------------------------------+ | RAX: 0 RCX: 0 RDX: 0 | | RBX: 0 RSP: f8 RBP: 0 | | RSI: 0 RDI: 0 R8: 0 | | R9: 0 R10: 0 R11: 0 | | R12: 0 R13: 0 R14: 0 | | used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f | +--------------------- (end of halted state) ---------------------------+