This page is for a prior offering of CS 3330. It is not up-to-date.
Note: a minor bug in HCL2D which could cause register file or memory values to sometimes be written before the end of a cycle was fixed on 2017-03-03 12:18. We think it is very unlikely that this bug will cause your processor to operate incorrectly, but we’d encourage you to re-download HCL2D.
This is a small homework to expose you to the hcl2d tool we’ll use for the next several labs and homeworks.
ir.hcl
To start exploring HCL, create a simulator that handles the irmovq
instruction and halt
.
icode
to ensure it is IRMOVQ
and also get rB
and valC
.IRMOVQ
, send valC
to the register file as the new value for register number rB
. If it is not IRMOVQ
, do not do this register write!HALT
, halt.If you run your simulator with the -q
flag on y86/irmovq.yo
, you should see
+----------------------- halted in state: ------------------------------+
| RAX: 222 RCX: 2 RDX: 22 |
| RBX: 0 RSP: 0 RBP: 0 |
| RSI: 0 RDI: 0 R8: 0 |
| R9: 0 R10: 0 R11: 0 |
| R12: 0 R13: 0 R14: fedcba9876543210 |
| register pP(N) { pc=0000000000000033 } |
| used memory: _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _a _b _c _d _e _f |
| 0x0000000_: 30 f0 01 00 00 00 00 00 00 00 30 f1 02 00 00 00 |
| 0x0000001_: 00 00 00 00 30 f2 22 00 00 00 00 00 00 00 30 f0 |
| 0x0000002_: 22 02 00 00 00 00 00 00 30 fe 10 32 54 76 98 ba |
| 0x0000003_: dc fe |
+--------------------- (end of halted state) ---------------------------+
Cycles run: 6
If you see 0
in RAX
instead of 222
it is likely that you’re writing to the register file for halt
as well as irmovq
.
Submit a file named ir.hcl
on the submission page.