- RISC v CISC
- ISA tradeoffs 
    - RISC: reduced complexity for the implemntor of the processor
        - veruss more convenience for compiler writers/assembler writers
        - "semanitc gap" --- how close the ISA is to the "real" language (C, Java, ...)
                - big for RISC
                - RISC processors typically don't have push/pop
                - "insert on linked list instruction --- easier for compiler
        - typically more registers --- why? do something with "Extra" hardware space
    - how much time it takes HW
    - how big (area/power/etc.) the HW is
    - size of programs ---  variable/fixed length; # of addressing mode
        RISC - more machine code for the same progrma
        CISC-like - less machine code for the same program
    - addressing modes: %rax, (%rax), 100(%rax), 100(%rax, %rbx)

- clock cycle
- register file control signals
    - things that happen at the rising of the edge of the clock:
            "end of a clock cycle"
        - all registers update:
            - PC register updates
            - register file stored values update
            - CC register updates
        - data memory completes write
    - things that happen as values are available: (within a clock cycle)
        - all computation
        - reading registers from the register file
        - reading memories

    - register file input/outputs:
        - reg# --- value (read this cycle or to write at next clock rising edge)
        - srcA --- outputA
        - srcB --- outputB
        - dstE --- inputE
        - dstM --- inputM
        - 4 bits --- 64 bits

- registers written/read by POP/PUSH
    - POP RX:
        R[RX] <- M[R[RSP]]
        R[RSP] <- R[RSP] + 8

    - PUSH RX
        M[R[RSP] - 8] <- R[RX]
        R[RSP] <- R[RSP] - 8
        
        

- endianness/memory access quesitons

    0x100: 0x12
    0x101: 0x34
    0x102: 0x56 / 0xCD
    0x103: 0x78 / 0xAB

    movl 0x100, %eax --- 
        l -- 32 bits
        %eax --- 32 bits
        4 bytes: 0x78 56 34 12

    movq $0xAB CD, 0x102
        0x102: 0xCD
        0x103: 0xAB
        0x104: 0x00
        0x105: 0x00
        ...
        0x109: 0x00

    2(%eax) --- memory at address: 2 + value in EAX