.c / .s / .o / .exe
    .c file -- contains C code (as ACII)
    .s file -- contains assembly code (as ASCII)
    .o file -- contains machine code and data
            -- with "holes" for memory locations
    .exe file -- contains machine code and data
               -- w/o "holes" for memor locations

RISC v CISC
    - key idea: RISC -- reduced complexity for the chip designer
        - not easier for compiler writers, assembly writers
        - not necessairily lower power (though some parts help)
            - but simplifying things tend to lower power/area
        - uniform decode 
        - fixed-length
        - seperate memory-accessing instructions (no POPQ/PUSHQ)
        - ?? more registers -- "something to do with same amount HW"
        - no "insert into linked list"

list conversions  and  malloc
heap versus stack
    - sentinel array:   ptr --->   {0, 1, 2,3, 4, SENTINEL}
        - ptr is on stack or in registers
        - thing it points to is malloc'd
            - one allocation, # elements + 1 element space
    - range: { len: 5; ptr ---> {0,1,2,3,4} }
        - struct range_t is on stack on in registers
        - thing it points is malloc'd
            - one allocation, # elements (no extra stuff malloc'd)
    - linked list: ptr -->  {payload: 0, next --> {payload: ....
        - ptr is on stack or in registers
        - one allocatoin for each node
        - extra space for one pointer for every node

    - stack -- where function-local data goes
            -- disappears at end of function
        "passed by value"
    - heap -- data that can survive past a function
            -- only allocated using malloc/realloc/calloc/operator new/etc.
            -- must be explicitly deallocated
        "passed by pointer"

5 stages of SEQ
clock cycles and timing
    - things that change at the rising edge of the clock cycle (end of a cycle)
        - values stored in the register file
        - values stored in registers like PC
        - vvalues stored in the data memory
    - things that happen during a clock cycle
        - any computation
        - reading a register from the register file
        - reading a value from a memory

    - stages --- CONCEPTUAL division of the processor into pieces of work
        - divide up work of *designing* hardware
        - doesn't say when things actually happen
    - Fetch (instr memory + split) / Decode (register file)  / Execute (ALU) / Mmeory (data memory) / Write back (write register file) / PC update


Fall 2016 Q20 -- bit-puzzles
    
    -x == ~x + 1

    X ? Y : Z --> if (X) Y else Z

C loops to ASM
ZF/SF
    ZF = 1 if zero
    SF = 1 if negative
        based on computed value
        cmpq --> subq (without storing non-condition code result)

    first: convert to if () goto
        
        while (x > 0) {
            foo();
            x += 1;
        }
   
        loop:
            if (!(x > 0)) { /* "guard condition" */
                goto endLoop;
            }
            foo();
            x += 1;
            goto loop;
        endLoop: 

        do {
            foo();
            x += 1;
        } while (x > 0);

        loop:
            foo();
            x += 1;
            if (x > 0)
                goto loop;