CS 3330: Spring 2016 Quizzes

This page is for a prior offering of CS 3330. It is not up-to-date.

This page contains quizzes given Spring 2016. For other semesters see the main old quizzes page

1 Spring 2016 Quiz 0

How are C and C++ related?
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Some of the tools we use in this class use strict ANSI-compliant C. You can get this version by running gcc -ansi -pedantic-errors or clang -ansi -pedantic-errors. In this standard one (and only one) of the following is an error. Which one?

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Suppose you have a variable declared as an array (e.g., int y[32]) and another declared as a pointer (e.g., “int *z“). In what way do the two variable differ?
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If we declare “int *x = malloc(16);" how many ints can fit inside x?
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2 Spring 2016 Quiz 1

Suppose a process spends 1 second doing task A, then 3 doing B, then 6 doing C. Which of the following will give the biggest speedup?
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Given some type T (where sizeof(T) ≠ 1) and a variable declared “T *x, which of the following is equivalent tox[3]“?
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Suppose I have a type declared “typedef struct range_t { int length; int *ptr; } range;" and a function declared range foo() that returns a range with length=8 and an 8-element heap-allocated array pointed to by ptr. How much heap memory does foo need to use? Select all that apply (i.e., the answer should be the sum of the options you pick).

How much memory is used to represent the string 3330 in C? Answer as an integer number of bytes (expressed in the usual base-10 format with no leading zeros). Ignore alignment and other nuances of memory that we have not discussed.

3 Spring 2016 Quiz 2

Reminder: in most C dialects, >> is a logical shift for unsigned types and an arithmatic shift for signed types

Suppose we have a signed char x. What is the numeric value stored in x after executing x = -1; x >>= 1;?
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Suppose we have an unsigned char x. What is the numeric value stored in x after executing x = -1; x >>= 1;?
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When doing arithmetic by hand in binary, which of the following binary operations are different for signed vs unsigned values? Assume (as all hardware I know of assumes) that the signed values are in 2’s compliment form.
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If we had a 3-byte (24-bit) floating point number with 18 exponent bits, how many of the 224 possible values of the floats would be NaN values? Answer with a non-negative integer written in base 10 with no leading zeros.



4 Spring 2016 Quiz 3


In ATT-format assembly (the default for gnu tools and our textbook), registers are prefixed by a %
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In ATT-format assembly (the default for gnu tools and our textbook), numerical immediate values are prefixed by a $
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While can be converted to assembly either as jump-to-middle or as guarded-do, the latter of which the book describes as enabling other optimizations. Without those extra optimizations, which one involves executing more instructions?
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The text discusses stack usage with call and ret, but this is mostly convention, not forced behavior. Which of the following jumps to an address stored in a register?
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5 Spring 2016 Quiz 4


Y86-64 is little-endian. What sequence of bytes would represent irmovq $0x1234, %r8? Answers are listed in hex
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Compare an rrmovq and a cmovXX with an unconditional fn
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Which of the following operand formats from x86 also exist in Y86? Select all that apply

Figure 4.2 does not include the encoding for a label. This is because
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6 Spring 2016 Quiz 5

While can be converted to assembly either as jump-to-middle or as guarded-do, the latter of which the book describes as enabling other optimizations. Without those extra optimizations, which one involves executing more instructions?
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The text discusses stack usage with call and ret, but this is mostly convention, not forced behavior. Which of the following jumps to an address that is stored in a register?
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Y86-64 has the following features. Select all that suggest Y86-64 is a RISC architecture:

In a little-endian machine, select all that apply:

7 Spring 2016 Quiz 6

Suppose we were creating an instruction ipushq that moves from an immediate to the stack. Figures 4.18 and 4.20 in the textbook describe irmovq (which moves from an immediate) and pushq (which moves to the stack). Using them as a reference, answer the following questions about how we would describe the behaviour of ipushq.


Suggestion: write out a full description of ipushq on paper and then answer the questions below.

irmovq and pushq both have a register byte (rA:rB ← M1[PC+1]) but each only use one of the two registers: irmovq only uses rB and pushq only uses rA. ipushq should
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irmovq does nothing in the decode stage; pushq does two things there (both valA ← R[rA] and valB ← R[%rsp]). What should be in ipushq’s decode stage?
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irmovq’s execute stage simply renames valC as valE (valE ← 0 + valC). The book has this renaming step because later in the chapter, when they turn these descriptions into actual muxes and wires, there isn’t a wire named valC in the writeback stage. pushq’s execute stage does some computation (valE ← valB + (−8)). ipushq’s execute stage should:
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irmovq does nothing during the memory stage; pushq writes the value it read from a register (valA) into memory (M8[valE] ← valA). ipushq’s memory stage should
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irmovq’s writeback is (R[rB] ← valE); pushq’s writeback is (R[%rsp] ← valE). ipushq’s writeback should be:
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8 Spring 2016 Quiz 7

Section 4.3.3 SEQ Timing emphasizes that (1) no stage depends on the results of a later stage and (2) no instruction reads a register or memory value after writing it. Which of the following would violate one of these two rules?
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irmovq moves from an immediate value (which can be found in valC) to the register file, but neither figure 4.23 nor the up-close view of memory in figure 4.28 has an arrow from valC to the register file. Why not?
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9 Spring 2016 Quiz 8


The main reason we add pipelining is to
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Suppose three people are making pies. A makes the crust and hands it to B, who adds the filling and hands it to C, who bakes it. If the three live in separate states and send their partially-completed pies via post, they all have a lot of down-time waiting for the pies to arrive. This inefficiency is called
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Suppose 26 people are making pies. A gets a bowl, B adds flour to it, C adds oil, D mixes, E gathers into a ball, … Y removes it from the oven, and Z puts it in a box. Each one’s task is so small that they spend more time moving back and forth than they do actually working. This inefficiency is called
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Suppose three people are making pies. A makes the crust and hands it to B, who adds the filling and hands it to C, who bakes it. If B requires twice as much time per pie as A and C, then A and C have a lot of down-time waiting for B. This inefficiency is called
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A generic register has two inputs: a single-bit clock and several-bit data input; it also has one output, a several-bit data output.

A pipeline register has the inputs of a generic register and also two one-bit inputs bubble and stall. We assume that it is never the case that both bubble and stall are 1.

The following questions assume G is a generic register with inputs {G.clock, G.input} and output {G.output}. They ask how to implement a pipeline register with inputs {bubble, stall, clock, input} and output {output} using G.


Generic registers only change output values on a rising clock edge. Which of the following can change the output of a pipeline register before a rising clock edge? Select all that apply.
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The bubble input should be used to implement pipeline control in what way? (The trinary operator ?: below has the same semantics it has in C.)

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The stall input should be used to implement pipeline control in what way? (The trinary operator ?: below has the same semantics it has in C.)
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10 Spring 2016 Quiz 9

In the context of chapter 4, a hazard is a characteristic of which of the following?
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In the context of chapter 4, a dependency is a characteristic of which of the following?
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Suppose we are executing a program containing instructions: i1, i2, i3, i4, … etc. Assume all of the instructions run in order and without jumps, stalls, dependencies, or hazards.  Assume the five-stage pipeline discussed in the textbook.

If i5 is in the execute (E) stage, what is in memory (M)?

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Suppose we are executing a program containing instructions: i1, i2, i3, i4, … etc. Assume all of the instructions run in order and without jumps or stalls. Assume the five-stage pipeline discussed in the textbook.

If we use data forwarding to get i5 through the execute (E) stage, we did which of the following?

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Suppose we are executing a program containing instructions: i1, i2, i3, i4, … etc. Assume all of the instructions run in order and without jumps or forwarding. Assume the five-stage pipeline discussed in the textbook.

If we use stalling to get i5 through the execute (E) stage, we did which of the following?

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11 Spring 2016 Quiz 10

If power is lost for 1 millisecond and then restored, which kind of RAM will still have its contents?
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Which of the following has the best temporal locality? Consider only data accesses, not instructions.
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Which of the following has the best spatial locality? Consider only data accesses, not instructions.
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Cache rhymes with
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Which of the following is blamed on the cache’s replacement policy?
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12 Spring 2016 Quiz 11

Dirty bits are associated with
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Given a byte-addressable memory with a 4GB address space; and a direct-mapped cache with 64-byte blocks and 16-bit tags; how many lines are there in the cache? Answer as a base-10 integer with no leading 0:

Suppose two set-associative caches (A and B) have the same total data capacity, same address size, and same block size, but cache A has twice as many lines per set as cache B. Which of the following is true?
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In a set-associative cache, which of the following does not impact the way an address is split into tag, index, and offset?
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13 Spring 2016 Quiz 12

For each code snippet below, assume that p and q each points to an array containing the first nine prime numbers (2, 3, …, 23). Select the answer(s) if and only if the code behaves the same both when p and q are aliases and when they are not aliases.

Which of the following best describes the intent of eliminating loop inefficiencies?
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Function inlining (described in an aside in section 5.1) is the ultimate solution to reducing procedure calls. In non-recursive code, it is possible to inline all procedures and have no procedure call overhead at all. Doing this is a bad idea because (select all that apply)

Which of the following does NOT appear to have an unneeded memory reference? Assume the program does some work between the two address accesses.
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14 Spring 2016 Quiz 13

Loop unrolling principally reduces what performance cost?
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Multiple Accumulators is listed under Parallelism, meaning pipeline parallelism. They help because
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Which of the following will be fastest?
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Register spilling is a bigger problem if
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Branch misprediction is a bigger problem if
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Profilers are particularly useful if
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15 Spring 2016 Quiz 14


All of the following are true for either Java or Hardware exceptions, and most are true of both; which one is only true of one of the two?

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For the following seven hardware exception concepts, pick the matching Java exception concept. Each of the seven answers is the correct answer to one of the seven questions.

Exception handler
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Exception number
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Exception table
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Interrupt
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Trap
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Fault
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Abort
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16 Spring 2016 Quiz 15

Consider two processes A and B. Which of the following is equivalent to the statement A and B are executing concurrently?
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Consider two processes A and B. Which of the following is equivalent to the statement A and B are executing in parallel?
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Signals are how
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Interrupts are how
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Traps are how
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17 Spring 2016 Quiz 16

Using virtual addresses,
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If each PTE is 8 bytes and each page is 4 KB, how large is a single-level page table for 30-bit addresses?
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A page table’s conceptual datatype (implemented by both single- and multi-level page tables) is
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A page table entry in a multi-level page table stores metadata (such as a valid bit) and
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To look up an address (not to access the data at the address, just to perform the address translation) using a three-level page table, the MMU needs to access memory
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18 Spring 2016 Quiz 17

If we extend the book’s comparison between caches and page tables, for a 48-bit virtual address with 4 KB pages and 40-bit physical addresses, how many bits long is the tag? Answer as a normal decimal integer:

The set index of an address going to a cache is like the _____ of a virtual address going to a page table
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Virtual memory can be thought of as using RAM as a cache for disk. Thought of in this way, virtual memory is
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Some page faults generate SIGSEGV (a.k.a. segfault) and others are handled without any problems. Which of the following can be handled without a SGISEGV?

19 Spring 2016 Quiz 18

Compare and contrast memory caching (where slow RAM and fast L# caches interact to provide the illusion of a large, fast memory) and virtual memory (where slow disk and fast RAM interact to provide the illusion of large, fast memory). Several questions refer to the faster store (meaning the L# cache for caches, the RAM for virtual memory) and the slower store (meaning RAM for caches, disk for virtual memory). Assume for these questions that caching is implemented on a computer without virtual memory and virtual memory is implemented on a computer without caching.

The table below summarizes the paragraph above:

  Memory Caching Virtual Memory
the faster store L# cache RAM
the slower store RAM Disk
assumptions: The computer has no virtual memory The computer has no memory caching
 
Anywhere it matters, assume the cache is set-associative and the virtual memory uses multi-level page tables

Requires an exception table to exist
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Code written assuming we have this would still work without it, though it may run more slowly
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Stores contiguous chunks of data in the faster store (to take advantage of spatial locality)
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Enables the enforcement of read-only memory
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Is used for all memory accesses (both in user and kernel mode)
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The same address always maps to the same location in the slower store
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The same address always maps to the same location in the faster store
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Copyright © 2016–2017 by Samira Khan, Luther Tychonievich, and Charles Reiss.
Last updated 2016-12-08 11:27:34