# Instructions Implemented: NOP, HALT, IRMOVQ, OPQ ########## the PC register ############# register pP { pc:64 = 0; } # Pipeline register between fetch/decode/execute and writeback register eW { icode:4 = NOP; Stat:3 = STAT_AOK; valC:64 = 0; dstE:4 = REG_NONE; valE:64 = 0; } ########## Fetch ############# pc = P_pc; wire ifun:4, rA:4, rB:4; e_icode = i10bytes[4..8]; ifun = i10bytes[0..4]; rA = i10bytes[12..16]; rB = i10bytes[8..12]; e_valC = [ e_icode in { IRMOVQ } : i10bytes[16..80]; 1 : 0; ]; wire offset:64, valP:64; offset = [ e_icode in { NOP, HALT } : 1; e_icode in { OPQ } : 2; e_icode in { IRMOVQ } : 10; 1 : 0; ]; valP = P_pc + offset; e_Stat = [ e_icode == HALT : STAT_HLT; e_icode > 0xb : STAT_INS; 1 : STAT_AOK; ]; ########## Decode ############# # source selection wire valA:64, valB:64; reg_srcA = [ e_icode in { OPQ } : rA; 1 : REG_NONE; ]; reg_srcB = [ e_icode in { OPQ } : rB; 1 : REG_NONE; ]; e_dstE = [ e_icode in { IRMOVQ, OPQ } : rB; 1 : REG_NONE; ]; valA = reg_outputA; valB = reg_outputB; ########## Execute ############# e_valE = [ e_icode == OPQ && ifun == ADDQ : valA + valB; e_icode == OPQ && ifun == SUBQ : valB - valA; e_icode == OPQ && ifun == ANDQ : valA & valB; e_icode == OPQ && ifun == XORQ : valA ^ valB; 1 : 0; ]; ########## Memory ############# ########## Writeback ############# # destination selection reg_dstE = [ W_icode in { IRMOVQ, OPQ } : W_dstE; 1 : REG_NONE; ]; reg_inputE = [ W_icode in { OPQ } : W_valE; W_icode in { IRMOVQ } : W_valC; 1 : 0; ]; ########## PC and Status updates ############# Stat = W_Stat; p_pc = valP;