This is the website for a prior semester's offering of CS 3330.

This page contains quizzes given Fall 2015. For other semesters see the main old quizzes page

Fall 2015 Quiz 01


In method main you declare an int variable named x. The compiler might place that variable in a register, or it could be in which region of memory?
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Accepted characters: numbers, decimal point markers (period or comma), sign indicators (-), spaces (e.g., as thousands separator, 5 000), "E" or "e" (used in scientific notation). NOTE: For scientific notation, a period MUST be used as the decimal point marker.
Complex numbers should be in the form (a + bi) where "a" and "b" need to have explicitly stated values.
For example: {1+1i} is valid whereas {1+i} is not. {0+9i} is valid whereas {9i} is not.

Suppose your code spends 80% of its time running function f. If you parallelize function f to run 4 copies at once, your code will now take what percentage of its previous time? Answer: %

Suppose you write multi-threaded code (does 2+ things at once) but run it on a single uniprocessor (does only one thing at a time, but swaps rapidly between threads to give the illusion of 2+ things happening at once). This situation exhibits
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Fall 2015 Quiz 02


Which of the following are true? Assume C notation. Select all that apply.

Accepted characters: numbers, decimal point markers (period or comma), sign indicators (-), spaces (e.g., as thousands separator, 5 000), "E" or "e" (used in scientific notation). NOTE: For scientific notation, a period MUST be used as the decimal point marker.
Complex numbers should be in the form (a + bi) where "a" and "b" need to have explicitly stated values.
For example: {1+1i} is valid whereas {1+i} is not. {0+9i} is valid whereas {9i} is not.

Consider an 1-byte IEEE-style floating-point number with 5 exponent bits and 2 mantissa bits. How many distinct bit patterns are NaNs for this number? Answer as an integer between 0 and 255

What is the smallest number of bits needed for an IEEE-style floating-point number to be able to represent the value 5 (binary 101)? Include a sign bit and use the standard bias (which is pow(2, exponentBits-1) - 1)
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The standard C method "rint" applies the current rounding mode to return the nearest integer value to a double. Using the default rounding mode and assuming that x is an integer, what is rint(x+0.5) - rint(x-0.5)?
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Fall 2015 Quiz 03

Our textbook and most GNU tools using ATT format assembly, but 2150 uses Intel format assembly instead. Each of the following is either true for ATT or Intel format, but not both; which are true of ATT format assembly? Select all that apply.

The textbook shows two ways to translate a while loop to use goto statements: jump to middle and guarded do. Optimizing compilers prefers guarded do. This is because
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The call instruction changes which of the following registers? Select all that apply.

Fall 2015 Quiz 04

Most jumps can only go to compile-time-known addresses, but the C switch command jumps to a runtime-computed address using jmp *label(offset) syntax x86-64 assembly. Which Y86-64 command moves the program counter to a runtime-computed address?
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Which of the following Y86-64 assembly snippets does the same thing as cmovle %rbx, %rax?

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The pushq operation (in either x86-64 or Y86-64) does which of the following?
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Fall 2015 Quiz 05

The C operators & and && function differently in that both (1) & is bit-wise but && is logical instead; and (2) && short-circuits, only evaluating the second operand if the first operand was true. The AND gates and HCL && operator described in the book
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The C operators & and && function differently in that both (1) & is bit-wise but && is logical instead; and (2) && short-circuits, only evaluating the second operand if the first operand was true. The AND gates and HCL && operator described in the book
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Supposed I have a register and want to be able to "stall" it, preventing it from storing new values when there is a 0 on wire X. While the register is stalled, I want it to keep whatever value it had when I stalled it until X has a 1 again, at which point it may resume normal operation. To do this, I should
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Supposed I have a register and want to be able to "bubble" it, such that if there is a 0 on wire X then it outputs a 0 no matter what its data input is. To do this, I should
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In the HCL described in the book, the square bracket notation
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Fall 2015 Quiz 06

Figure 4.18 of the textbook gives a sequential implementation of the Y86 instruction OPq. Suppose we wanted to have a *new* operator in Y86, iOPq, in which one of the two operands was an immediate value and the other was a register. The questions below give pieces of OPq and ask about changes associated with implementing iOPq.

OPq's description has the line "icode:ifun ← M1[PC]". True or False: we'd have to change that line in some way for iOPq.
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OPq uses two registers, rA and rB. iOPq only needs one register; which one should we keep?
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OPq increments the PC by 2 in the line "valP ← PC + 2"; iOPq would use what increment?
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OPq has the execute step "valE ← valA + valB"; assuming we don't change decode, we should replace one of the two operands (either valA or valB) with
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The textbook has the line "Set CC" as part of OPq's execute step. If we were to omit that line from iOPq, which one of the following would be true?
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Fall 2015 Quiz 07

Consider adding a new instruction "jpr" to SEQ that jumps to a program register. A use of the instruction might look like "jpr %rdi"

When fetching JPR we'd set need_valC to true.
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In the new_pc mux on page 411 (page 390 of the 2nd edition), we should
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What (if anything) needs to change about the execute mux that sets aluA on pages 408 and 409 of the textbook (page 388 of the 2nd edition)?
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JPR would access data memory (either to read or write)
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The register file has six inputs: two read ports accessed with one input each and two write ports accessed by a pair of inputs. How many of these six inputs are used by JPR? (note: setting them to some kind of NOT_USED value does not count as using them)
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Fall 2015 Quiz 08

Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a single-instruction program run faster?
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Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a 50-instruction program run faster?
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Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will
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Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will
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If registers had no delay at all,
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Fall 2015 Quiz 09


Which of the following are features of hardware? Select all that apply.

Which of the following are features of software? Select all that apply.

Each logical stage in a pipeline lies between two pipeline registers. Suppose we have stages S1, S2, and S3 and registers R1 and R2 laid out like S1→R1→S2→R2→S3. Note: part of this question depends on the fact that "bubble" and "stall" mean different things when applied to register (like R1) vs stages (like S1).

If we want to *stall* S2, what control signal do we give to R1?
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If we want to *stall* S2, what control signal do we give to R2?
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If we want to *bubble* S2, what control signal do we give to R1?
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If we want to *bubble* S2, what control signal do we give to R2?
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If we want to *bubble* S2, what do we need to do to S1?
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If we want to *bubble* S2, what do we need to do to S3?
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Fall 2015 Quiz 10

Static RAM is typically faster than dynamic RAM
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Static RAM is typically cheaper than dynamic RAM
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Which kind of RAM needs to be read and re-written to retain its value?
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Which kind of RAM retains its value if power is lost?
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(data memory) Temporal locality is when
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(data memory) Spatial locality is when
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Fall 2015 Quiz 11

Which of the following implements a single array of lines?
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Which of the following implements a single set of lines?
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Given 64-bit addresses, 8-byte blocks, 4-element sets, and 16 sets, how long is the tag? Answer as a positive base-10 integer like 3 or 127.

The dirty bit is used for (pick the best answer)
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A conflict miss is when
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Which of the following is likely to increase the cache-friendliness of code the most?
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Fall 2015 Quiz 12

(section 5.1) Why do twiddle1 and twiddle2 not get the same optimization?
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(section 5.2) The textbook's CPE (cycles per execution) is about
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(section 5.4) The core idea of "eliminating loop inefficiencies" is to
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(section 5.5) Why does reducing procedure calls save us time?
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(section 5.8) Loop unrolling primarily benefits us by
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Fall 2015 Quiz 13

Which of the following terms is a general term that includes the others as sub-kinds?
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Which of the following refers to something created by an event external to the CPU?
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Which of the following is always created intentionally by user code?
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Which of the following is handled by the exception table?
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Fall 2015 Quiz 14

Let C be the set of all possible concurrent processes and P be the set of all possible parallel processes.
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If you run two programs at the same time and the two use the same addresses,
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Most processors contain a special one-bit register called the "mode bit" that distinguishes between kernel mode and user mode. True or false: when in user mode, programs can run some but not all of the assembly instructions they can run in kernel mode.
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True or false: when in user mode, programs can access some but not all of the addresses that they can access in kernel mode.
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True or false: when in user mode, programs can access some but not all of the file system locations that they can access in kernel mode.
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Which of the following will not cause a context switch?
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Fall 2015 Quiz 15

Select all that apply:

In caches the fundamental unit of storage is a line or block. In virtual memory it is a ____ (give a one-word lower-case answer without punctuation)

(select all that apply) A PTE describes where a particular range of addresses in virtual memory is stored. It can be

A page fault is a type of exception, as described in chapter 8
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A PTE describes where a particular range of addresses in virtual memory is stored, as well as all but one of the following; which one is not part of PTE?
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Fall 2015 Quiz 16

The page table maps between virtual and physical addresses; it is stored
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The PTBR contains an address. This address is in a
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A page table is used like an array; its index is
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A TLB is
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For multi-level page tables, each process has several page tables for its memory. What is the size of each of these page tables?
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Fall 2015 Quiz 17

Compare and contrast memory caching (where slow RAM and fast L# caches interact to provide the illusion of a large, fast memory) and virtual memory (where slow disk and fast RAM interact to provide the illusion of large, fast memory). Several questions refer to "the faster store" (meaning the L# cache for caches, the RAM for virtual memory) and the "slower store" (meaning RAM for caches, disk for virtual memory). Assume for these questions that caching is implemented on a computer without virtual memory and virtual memory is implemented on a computer without caching.

The table below summarizes the paragraph above:

  Memory Caching Virtual Memory
"the faster store" L# cache RAM
"the slower store" RAM Disk
assumptions: The computer has no virtual memory The computer has no memory caching

Involves cooperation between OS and HW
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Values in the faster store are also in the slower store
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Would increase addressable space even if the faster store and slower store were the same size
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Would provide a benefit other than more addressable space even if the faster store and slower store were the same size
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Generates a fault on a miss
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The same address always maps to the same location in the slower store
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The locations in the various stores are computed using pieces of the memory address being accessed
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The locations in the various stores are computed using the contents of one or more of the stores
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Regarding the mapping between slower-space addresses and faster-space addresses, virtual memory is most like which kind of cache?
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