This page contains quizzes given Spring 2015. For other semesters see the main old quizzes page

Spring 2015 Quiz 1

: Which two of the following four binary number formats are used by modern computer hardware?
A. one's-complement integer
B. sign-magnitude integer
C. two's-complement integer
D. unsigned integer

: Binary 0011 + binary 1001 = ____ (answer in binary with exactly four characters, each either 0 or 1)

: 0x3f ^ 0x15 = ____ (answer in lower-case hexidecimal with exactly two characters, each between 0 and f)

: Which of the following is true for all possible values of unsigned x?
A. !!x == x
B. !!x == ((x<<31)>>31)
C. (x+x) > x
D. (x^(x+1)) == 1
E. x + 1 > x
F. more than one of the above is true for all x
G. none of the above are true for all x
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Spring 2015 Quiz 2

If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, which of the following numbers (shown in binary) is the largest finite number it can represent?
A. 1.11
B. 1.111
C. 11.1
D. 11.11
E. 111.0
F. 111.1
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If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, what is the smallest positive number (> 0) it can represent? Answers are shown in binary
A. 0.001
B. 0.0001
C. 0.00001
D. 0.000001
E. none of the above
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Consider the following eight binary C operators: + - * / % ^ & |. Consider the 32 bits representing the result of "x operator y", where x and y are each either int or unsigned int. For how many of these 8 operators will those bits differ depending on the singed/unsigned nature of x and y? Your answer should be a single digit between 0 and 8:

Spring 2015 Quiz 3

How many total bytes of data can be stored in the (integer) IA32 program registers at one time? (a program register is one you can use as an operand when in programming in IA32 assembly)
A. 4
B. 8
C. 16
D. 32
E. 48
F. 56
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The textbook uses ATT-format assembly, the default for most GNU tools. Some other tools use Intel-format assembly instead. Each of the following is true for only one of the two formats. Check those that are true of ATT-format assembly:
A. there is a separate opcode for adding 32-bit values (addl) and 16-bit values (addw)
B. register names are preceded by a percent-sign (e.g. %eax)
C. memory addresses are written with square brackets and math operators (e.g. [edx+4])
D. add A B (where A and B are registers) stores the sum of A and B into register A
E. sub A B (where A and B are registers) evaluates B - A, not A - B

"pushl %eax;" is the same as
A. addl \$4 %esp; movl %eax (%esp);
B. addl \$-4 %esp; movl %eax (%esp);
C. movl %eax (%esp); addl \$4 %esp;
D. movl %eax (%esp); addl \$-4 %esp;
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The "imul" instruction has only one operand, as in "imul \$101;", but the multiplication operation is implements requires two operands. The second operand is
A. %eax
B. %esp
C. (%esp)
D. 12(%ebp)
E. the same as the first (i.e., imul squares its operand)
F. none of the above
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Spring 2015 Quiz 4

In Java, C++, etc, there are types: a String is not the same as a Scanner, and so on. Types are distinct from "meaning": int x might *mean* your age and int y might *mean* your number of siblings, but the language doesn't stop you from saying "x = y" because they are both *type* int. In assembly
A. There are no types at all
B. Integers and floating-point numbers are distinct, but otherwise no types
C. There are only a few built-in types, but assembly lets you create new ones
D. There types like other languages have
E. There are more types than most other languages
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IA32 (also called x86) is CISC, not RISC, because (check all that apply)
A. each instruction takes the same time to execute
B. it has a lot of instructions or opcodes
C. math operations can only operate with register operands (not memory)
D. some instructions are encoded in just a single byte while others are much longer
E. some instructions provide high-level abstractions, hiding lots of action under the hood
F. there are many program registers

Spring 2015 Quiz 5

Two of the following are equivalent to the single-bit mux that the book denotes [ s : A; 1 : B; ], the other two are not equivalent to that mux. Mark the two that are:
A. (s == A) || (s ^ B)
B. (s == (A && B)) || (s != (A || B))
C. s ? A : B
D. (s && A) || (!s && B)

Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware retrieve the value stored in register %edx?
A. Fetch
B. Decode
C. Execute
D. Memory
E. Writeback
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Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware decide where the result will be stored?
A. Fetch
B. Decode
C. Execute
D. Memory
E. Writeback
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Not all stages are invovled in executing all instructions. Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. Which (if any) stages are not involved in handling this instruction? Check any that apply
A. Fetch
B. Decode
C. Execute
D. Memory
E. Writeback

Spring 2015 Quiz 6

Which of the following operations read a value from memory? Check all that apply
A. nop
B. rrmovl
C. irmovl
D. rmmovl
E. mrmovl
F. OPl
G. jXX
H. call
I. ret
J. pushl
K. popl

Which of the following operations write a value to memory? Check all that apply
A. nop
B. rrmovl
C. irmovl
D. rmmovl
E. mrmovl
F. OPl
G. jXX
H. call
I. ret
J. pushl
K. popl

Which of the following operations write a value to a program register? Check all that apply
A. nop
B. rrmovl
C. irmovl
D. rmmovl
E. mrmovl
F. OPl
G. jXX
H. call
I. ret
J. pushl
K. popl

Which of the following operations read a value from a program register? Check all that apply
A. nop
B. rrmovl
C. irmovl
D. rmmovl
E. mrmovl
F. OPl
G. jXX
H. call
I. ret
J. pushl
K. popl

The book discusses using the ALU just to forward values for some operations (e.g., their irmovl has the ALU compute 0 + valC) and to do math for other operations. The forwarding is just a design choice and could have been done otherwise, but the math is intrinsic to the operation of Y86. Which of the following operations use the ALU to do math?
A. nop
B. rrmovl
C. irmovl
D. rmmovl
E. mrmovl
F. OPl
G. jXX
H. call
I. ret
J. pushl
K. popl

When building a chip, we can pick any clock speed we want; the goal is to make it as fast as we can while still being slow enough that no register grabs onto a value before that value has stabilized. Which of the following instructions would be most likely to determine the SEQ clock speed?
A. nop
B. rrmovl
C. OPl
D. jXX
E. popl
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Spring 2015 Quiz 7

In general, pipelining
A. decreases latency and decreases throughput
B. decreases latency and increases throughput
C. increases latency and decreases throughput
D. increases latency and increases throughput
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Nonuniform partitioning happens when
A. in some stages, the clock cycle is longer than the stage requires
B. some stages have more work to do than others
C. work cannot be evenly divided between registers
D. all of the above
E. none of the above
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Suppose instruction A is followed by instruction B in the assembled code. There is a hazard between A and B if (check all that apply)
A. A's inputs depend on B's outputs
B. B's inputs depend on A's outputs
C. Whether A runs depends on the outcome of B
D. Whether B runs depends on the outcome of A

In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "stall" signal?
A. 0
B. 1
C. 2
D. 3
E. 4
F. 5
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In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "bubble" signal?
A. 0
B. 1
C. 2
D. 3
E. 4
F. 5
Reset Selection

Spring 2015 Quiz 8

Which of the following is orders from slowest to fastest?
A. Magnetic disk, Solid-state disk, DRAM, SRAM
B. Magnetic disk, Solid-state disk, SRAM, DRAM
C. Solid-state disk, Magnetic disk, DRAM, SRAM
D. Solid-state disk, Magnetic disk, SRAM, DRAM
E. None of the above is the correct ordering
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Data can be stored in program registers, memory, or disk. Which of the following technologies (if any) is/are most commonly associated with memory? Check all that apply
A. D Flip-flops
B. DRAM
C. Ethernet
D. Magnetic disk
E. Solid-state disk
F. SRAM

Which of the following needs to be read and then re-written periodically in order to retain its storage? Check all that apply
A. DRAM
B. Magnetic disk
C. Solid-state disk
D. SRAM

Which of the following needs power in order to retain its storage? Check all that apply
A. DRAM
B. Magnetic disk
C. Solid-state disk
D. SRAM

Spring 2015 Quiz 9

Code has good spatial locality if
A. each memory read is far from the address of the previous read
B. each memory read is near the address of the previous read
C. it uses a lot of memory overall
D. it uses little memory overall
E. there are gaps of unused memory padding the parts of memory it uses
F. there are no gaps of unused memory between parts of memory it does use
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Code has good temporal locality if
A. it accesses each memory location only once
B. some memory is accessed repeatedly, and all accesses happen one after the other
C. some memory is accessed repeatedly, and each access happens some time after the others
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Which of the following describes the kind of caching that the memory hierarchy implements?
A. after computing a value once, you store the result in memory to prevent having to compute it again later
B. once there is a market for your assets you sell them
C. you keep many copies of your data in different locations so that if one system fails you don't loose it all
D. you store most of your data in big, cheap memory but the most important stuff gets backed up onto a smaller, more expensive, but more durable memory
E. all of the above describe memory hierarchy caching
F. none of the above describe memory hierarchy caching
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Section 6.4 talks about blocks, caches, lines, and sets. Which one is contained by which other? Answer with four capital letters (B, C, L, and S) concatenated from outermost-to-innermost; for example, if believe that blocks contain caches which contain lines which contain sets, your answer should be BCLS

In a set-associative cache, which of the following can be determined from the memory address and cache organization alone (i.e., without knowing the cache contents)? Check all that apply.
A. block offset
B. set index
C. tag
D. which byte in the cache to access
E. which line in the cache to access
F. which set in the cache to access
G. valid bit

Quiz 10 was not given

Spring 2015 Quiz 11

Which of the following is expected to run fastest? Assume N and M are large numbers.
A. for(i=0; i<M; i+=1) for(j=0; j<N; j+=1) sum += a[i][j]
B. for(j=0; j<N; j+=1) for(i=0; i<M; i+=1) sum += a[i][j]
C. they're the same
D. it depends on the cache organization (associativity, etc)
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Which of the following is expected to run fastest? Assume N is a large number.
A. for(i=0; i<N; i+=1) for(j=0; j<N; j+=1) b[j][i] = a[i][j]
B. for(i=0; i<N; i+=1) for(j=0; j<N; j+=1) b[i][j] = a[j][i]
C. for(j=0; j<N; j+=1) for(i=0; i<N; i+=1) b[j][i] = a[i][j]
D. for(j=0; j<N; j+=1) for(i=0; i<N; i+=1) b[i][j] = a[j][i]
E. they're the same
F. it depends on the cache organization (associativity, etc)
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Which of the following are *not* tips for optimizing memory accesses given in the textbook? Check all that apply
A. focus on the common case
B. focus on inner loops
C. get in the habit of performing cache optimizations everywhere
D. reduce cache misses even if it means a few more memory accesses
E. try to read memory in sequential order
F. try to use data as often as possible once it has been read into memory

Spring 2015 Quiz 12

We want to loop over all i, j, and k (between 0 and 10240) and run the following: a[i][j] = b[i][k] * c[k][j] In order to maximize cache locality, in what order should the loops be placed?
A. for(i) for(j) for(k)
B. for(i) for(k) for(j)
C. for(j) for(i) for(k)
D. for(j) for(k) for(i)
E. for(k) for(i) for(j)
F. for(k) for(j) for(i)
G. it doesn't matter
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Which of the following is describes the situations in which you should optimize your code for cache locality?
A. always
B. never
C. any time it doesn't make code less readable
D. none of the above is correct
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Using a #define IDX (like those shown in class) and a 1D array instead of a 2D array is done because
A. it is easier to create a 1D array
B. it is easier to read code with IDX
C. it wastes less space
D. it ensures locality of neighboring rows
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Spring 2015 Quiz 13

Suppose function A is O(n) and for n=1 takes 100ms; function B is O(n^2) and for n=1 takes 1ms. Which of the following n do you expect to be the smallest for which A is faster than B?
A. 2
B. 20
C. 200
D. 2000
E. A is always faster than B
F. A is never faster than B
G. insufficient information to tell
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Register spilling is when
A. quantum effects cause register values to pollute one another
B. the value in a register gets so large it spills over into another register too
C. the value in a register gets to large it spills over the end of the register, causing some bits to be lost
D. there are so many local variables that some of them cannot be stores in registers
E. you run out of space in memory so you store some values in registers instead
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Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
A. x1 * x2 * (x3 * x4)
B. x1 * (x2 * x3) * x4
C. (x1 * x2) * x3 * x4
D. They're all the same
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Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
A. for(i=0; i<99; i+=1) a[i] = i;
B. for(i=0; i+1<99; i+=1) { a[i] = i; i+=1; a[i] = i; } a[98] = 8;
C. for(i=0; i+3<99; i+=1) { a[i] = i; i+=1; a[i] = i; i+=1; a[i] = i; i+=1; a[i] = i; } for(; i<99; i+=1) a[i] = i;
D. They're all the same
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Spring 2015 Quiz 14

If a virtual page is allocated and in physical memory, how do we discover the physical page number?
A. It's the same as the virtual page number
B. The MMU finds it in a page table
C. The operating system assigns it after loading the page from disk
D. The operating system finds it in a page table
E. We don't; there is no physical page number in this situation
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If a virtual page is allocated but is not in physical memory, how do we discover the physical page number?
A. It's the same as the virtual page number
B. The MMU finds it in a page table
C. The operating system assigns it after loading the page from disk
D. The operating system finds it in a page table
E. We don't; there is no physical page number in this situation
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If a virtual page is not allocated, how do we discover the physical page number?
A. It's the same as the virtual page number
B. The MMU finds it in a page table
C. The operating system assigns it after loading the page from disk
D. The operating system finds it in a page table
E. We don't; there is no physical page number in this situation
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Spring 2015 Quiz 15

Page tables are stored in
A. a special bank of registers
B. a special memory chip set aside for page tables
C. each process's virtual address space
D. main memory's physical address space
E. the page table base register (PTBR)
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If you have a single-level page table, the amount of space it requires varies based on how many pages are in use.
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If you have a multi-level page table, the amount of space it requires varies based on how many pages are in use.
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If your program uses 100% of the virtual address space (even the parts normally not used), having a multi-level page table requires
A. less space than a single-level page table
B. more space than a single-level page table
C. the same amount of space as a single-level page table
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If your program uses only a small fraction of the virtual address space, having a multi-level page table requires
A. less space than a single-level page table
B. more space than a single-level page table
C. the same amount of space as a single-level page table
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Spring 2015 Quiz 16

Section 9.7.2 talks about how linux keeps track of memory regions with regard to read/write/execute permissions and shared memory. That information is also in the page table entries. Why should there be vm_area_structs if the same information is in the page table?
A. having two copies provides fault tolerance if one fails
B. one is for read/write/execute permissions, the other for user/kernel permissions
C. one is for the MMU, the other for the OS
D. the vm_area_struct is how you access a page table entry in C
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Section 9.9 reviews how malloc and free work. One implementation of malloc and free has free do nothing and malloc simply keep a single pointer it increments each time it is called. This implementation has
A. high throughput and high utilization
B. high throughput and low utilization
C. low throughput and high utilization
D. low throughput and low utilization
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Section 9.10 discusses garbage collector. These often perform reachability analysis, tracing all pointers recursively to find what parts of allocated memory are actually usable. The reachability analysis starts assuming that what is reachable?
A. the most recent n allocation for some constant n
B. the pointers in every stack frame ever allocated
C. the pointers in every stack frame pushed but not yet popped
D. the pointers in the current stack frame
E. the pointers in the heap
F. the pointers in the heap that have been allocated but not yet deallocated
G. the pointers in the heap that have ever been allocated
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Spring 2015 Quiz 17

A cache maps an address to a value. Virtual memory maps an address to another address. Which kind of cache is virtual memory (i.e., page tables, not the TLB) organized the most like?
A. direct-mapped
B. set-associative
C. fully-associative
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Let V be the size of the virtual address space and P be the size of the physical memory. Which of the following is true?
A. V < P
B. V <= P
C. V == P
D. V >= P
E. V > P
F. any of the above could be true
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A page table entry contains some permission information and some type of pointer. If our program is trying to dereference a 32-bit integer value stored in memory, page tables accessed along the way could point to (select all that apply)
A. a page of data
B. another page table
C. some part of disk
D. the 32-but integer in question

Spring 2015 Quiz 18

Which type of exception does *not* use the exception table?
A. fault
B. interrupt
C. trap
D. all of the above use the exception table
E. none of the above use the exception table
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Which type of exception can occur without any particular instruction being the cause of the exception?
A. fault
B. interrupt
C. trap
D. all of the above can occur without any particular instruction being the cause of the exception
E. none of the above can occur without any particular instruction being the cause of the exception
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Which type of exception has an instruction that always causes it?
A. fault
B. interrupt
C. trap
D. all of the above have an instruction that always causes it
E. none of the above have an instruction that always causes it
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Which type of exception has an instruction that sometimes causes it and sometimes runs without causing it?
A. fault
B. interrupt
C. trap
D. all of the above have an instruction that sometimes causes it and sometimes runs without causing it
E. none of the above have an instruction that sometimes causes it and sometimes runs without causing it
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