Our graph-based approach to routing entails modeling the FPGA architecture as a graph; thus components of the FPGA are denoted by vertices and edges (pairs of vertices) in the routing graph (See example). These components are denoted as follows:

• Logic-block pins are vertices having the numbering format L.a.b.c.0, where a is the logic-block row, b is the logic-block column, and c is the logic-block pin (the trailing 0 adds no useful information).
• Vertical-channel segments are edges made up by two vertical-channel nodes, each node having the numbering format V.a.b.c.0, where a is the vertical-channel row, b is the vertical-channel column, c is the vertical-channel segment (numbered 0 through W - 1 for channel width W), and c is either 0 or 1, specifying either an upper-endpoint node or lower-endpoint node, respectively.
• Horizontal-channel segments are edges made up by two horizontal-channel nodes, each node having the numbering format H.a.b.c.0, where a is the horizontal-channel row, b is the horizontal-channel column, c is the horizontal-channel segment (numbered 0 through W - 1 for channel width W), and c is either 0 or 1, specifying either a left-endpoint node or right-endpoint node, respectively.
• Switch-block edges are denoted by pairs of vertical-channel and horizontal-channel nodes.