BenchmarkCircuit Labeling Format
Our graphbased approach to routing entails modeling the FPGA architecture
as a graph; thus components of the FPGA are denoted by vertices and edges
(pairs of vertices) in the routing graph
(See example).
These components are denoted as follows:

Logicblock pins
are vertices having the numbering format
L.a.b.c.0, where
a is the logicblock row,
b is the logicblock column, and
c is the logicblock pin
(the trailing 0 adds no useful information).

Verticalchannel segments
are edges made up by two verticalchannel nodes,
each node having the numbering format
V.a.b.c.0, where
a is the verticalchannel row,
b is the verticalchannel column,
c is the verticalchannel segment (numbered 0 through
W  1 for channel width W), and
c is either 0 or 1, specifying either an
upperendpoint node or lowerendpoint node, respectively.

Horizontalchannel segments
are edges made up by two horizontalchannel nodes,
each node having the numbering format
H.a.b.c.0, where
a is the horizontalchannel row,
b is the horizontalchannel column,
c is the horizontalchannel segment (numbered 0 through
W  1 for channel width W), and
c is either 0 or 1, specifying either a
leftendpoint node or rightendpoint node, respectively.

Switchblock edges
are denoted by pairs of verticalchannel and horizontalchannel nodes.