Adaptive Cache Decay using Formal Feedback Control

S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron.
In Proc. of the 2002 Workshop on Memory Performance Issues, in conjunction with ISCA-29, May 2002, Anchorage, Alaska.

This paper argues that adaptive techniques in processor architecture should be designed using formal feedback-control theory. We use the derivation of a controller for cache decay--a technique for leakage-energy savings--to illustrate the process of formal feedback-control design and to show the benefits of feedback control. Control theory provides a powerful framework that simplifies the task of designing an adaptive system. It provides well-known control designs that are easy to tune for performance and stability. Open-loop adaptation, on the other hand, is vulnerable to unacceptable behaviors when presented with workloads or conditions that were not anticipated at design time. In contrast, feedback control responds to unanticipated behaviors and provides robust operation in cases where open-loop designs fail. Since interest in adaptivity only continues to grow, the need for feedback control techniques and formal design techniques can only grow accordingly. Although our work so far leaves several open questions--especially the question of how best to choose the control setpoint--we hope that this paper will demonstrate the value of formal feedback control and provide guidelines for its general application in architecture research.

Available in ps or pdf