In comp.arch you write:
> (It seems clear to me that
>this is really a 25 MHz machine, marketing drivel notwithstanding).
Each to his own. For my applications, all of them, it's 50Mhz.
>My 'stream' benchmark shows a sustained performance of 43.6 MB/s for
>copying 64-bit numbers. Assuming that the HP cache reads in the line
>containing the destination before I write it, that means that the
>memory system is doing 3/2 times this, or 65.4 MB/s. This is only 1/3
>of the rated performance.
I think that you might be tripping on the next cache-line prefetch that
the system controller does. After a miss has been satisfied from
memory, the controller reads the next line into a buffer from where it
is supplied if it's the next miss. If it's not, then the buffer's
thrown away. As I remember your programs, that's an extra 8 bus cycles
for each cache miss.
The usual source fiddles would fix this, but I suspect that if you keep
making as much noise about it as you have then HP might fix the
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