720 Memory Bandwidth

From: Craig Gleason (cag@hpescag.fc.hp.com)
Date: Thu Jan 23 1992 - 09:54:01 CST

>The HP9000/720 blurb that I have says that the main memory to cache
>bandwidth is "200 MB/s for the duration of a 64-byte transfer". It
>also says that the bus is 64 bits wide. Dividing this through says
>that the bus frequency is (200 MB/s / 8 bytes/cycle) = 25 MHz, or
>one half of the nominal cpu clock speed. (It seems clear to me that
>this is really a 25 MHz machine, marketing drivel notwithstanding).

You can check the 1991 CompCon and ICCD proceedings for papers on the
processor and memory systems. There are three pieces to the path you're
talking about: The DRAM <-> memory controller bus, the memory controller
<-> processor bus, and the processor <-> (I/D) cache connections. The
DRAM bus is actually 64 bits wide and runs at 25MHz. The memory control
to processor bus is 32 bits wide and runs at 50MHz. The cache buses are
32 bits (I) and 64 bits (D). Cache writes are done two (32 bit words) per
three cycles on the I-cache and one (64 bit doubleword) per two cycles on
the D-cache. It really is a 50MHz machine.

The weird copy-in timing was used because we optimized the caches for
read timing and would have had to use faster SRAM parts to run the writes
at the same frequency (so why not just run the reads faster since they
tend to limit performance more than writes?).

The other decisions were made based on pin counts and time to market.
We were taking the processor we use in our 9000/870 multiprocessors and
re-working it as a single chip workstation CPU (with about a 12 month
schedule from design start to first silicon). The memory controller
was designed to work with the new processor. With the two chip design,
we couldn't get the wide buses of the RS/6000.

It's really a question of whose applications to focus on. We took the
approach that you should focus on the majority of applications that are
CPU intensive and will run cache-resident most of the time. IBM took more
of a high end approach and designed a really good memory connection. Their
price was a 6-9 chip set and no low end box. Ours was that we lose out on
the most memory intensive applications.

I have a 720 on my desk, and it's blazing fast for anything I do (primarily
X, vi and EE CAD).

Craig Gleason

This archive was generated by hypermail 2b29 : Tue Apr 18 2000 - 05:23:02 CDT