In COA1, you learned about transistors and gates connected by wires. These wires could have multiple destinations, but only one source. The single-source design limitation is important for efficient transistor-level design, but makes extending a system by adding new components challenging if not impossible.

1 Channel characterization

This writeup provides a brief description of a several connection types, organized from simplest to most flexible.

Some general terminology:

A medium capable of transmitting information. Wires, fiber optic cables, and radio frequency bands are examples of channels.
Information conveyed through a channel. Voltage changes, photons, and sound waves are examples of signals.
Data conveyed via signals on a channel. 1 and 0, songs, text, and pictures are examples of messages.
A party or device converting messages into a signal and placing it on a channel.
A party or device noticing a signal on a channel and converting it back into messages.

1.1 Simplex

In simplex communication, information only flows in one direction: receivers are not also senders. Wires between transistors and gates are simplex. So are broadcast radio, baby monitors, surveillance cameras, and streaming video.

Simplex communications generally require separate designs for the sender and receiver. Most simplex communication systems allow a message to be delivered to many receivers via the same signal.

If multiple parties try to send information on a simplex channel at the same time, a collision occurs. This is almost always bad, varying from confusion (as when two radio stations overlap) to destruction (as when two transistors connect to the same output wire, creating a short and burning the chip). Because simplex systems have no way to send back-and-forth data, collision is difficult to avoid if multiple sources exist.

1.2 Half-duplex

In a half-duplex system, every sender is also a receiver, but only one may place a signal on the channel at a time. Conversations can be seen as such a system: sound travels though shared air, but if both speak at once neither can understand the other.

Half-duplex systems typically require some type of protocol for resolving who gets to use the channel when and for how long. Because that protocol may mean that the channel might not be available when a sender wishes to use it, there is often a need to queue messages until the channel is available for sending.

1.3 Full-duplex

In a full-duplex system, every sender is also a receiver, and every party may send at the same time without messages being lost. Voting by raised hands can be seen as such a system: one person’s raised hand does not prevent another person’s lowered hand from being simultaneously visible, and each can both send and receive information simultaneously.

Full-duplex channels are generally implemented as one simplex channel per potential sender/receiver pair. In the raised hands example, the line-of-sight channel between a given sender’s hand and receiver’s eyes form that simplex channel. Because of this, full-duplex systems do not scale to an arbitrary number of parties.

Even if extremely large full-duplex channels can be created, their efficacy is limited by the processing needed to receive many messages. If instead of raising hands, everyone had a digital screen and flipped through text-heavy slides, the limiting factor would be how many messages each receiver could process, not the number of screen-to-eye simplex channels we could create.

1.4 Duplexing

Duplexing, also known as full-duplex emulation, is the process of using a protocol over a half-duplex channel to simulate full-duplex communication. Duplexing always involves delays in message delivery, but can provide the illusion of messages traveling simultaneously in both directions, though at a slower pace than the channel would be able to support in half-duplex mode.

There are many methods of duplexing possible. Alternating bytes from each sender is one of the simplest to describe, but more complicated approaches can be more efficient in most situations.

2 Network topology

The way that channels are used to connect many components can be characterized by its topology. There are many named topologies and many more unnamed or idiosyncratic topologies; three topologies will suffice for this overview.

The channels used to connect components in a network are traditionally called links.

2.1 Fully-connected

If every pair of components has a link between then, the network is said to be fully connected. For n components, that means \sum_{i=1}^ni=\frac{n(n-1)}{2} separate links.

While fully-connected networks provide arbitrary communication, they are expensive to construct at scale. Adding an additional component to a fully-connected network requires adding another link to each existing component, which is often impractical. Fully-connected networks are uncommon except in small networks with a limited, unchanging number of nodes.

2.2 Star

If there is one central component that is connected to every other component, the network is said to be a star and the component all others connect to is called the hub. For n components, that means n-1 separate links.

Star networks are simple to design, implement, and extend. However, they are highly dependent on the hub, being limited by its capabilities and going down if it does.

2.3 Bus

If every component is attached to the same half-duplex channel, the network is said to have a bus topology and that single channel is called the bus. For n components, that means 1 link.

Buses are relatively simple to construct but need to handle the potential for collision in some way. Adding new components to a bus is straightforward, but the likelihood of collision increases as more components are attached to the channel, so buses are good for situations when a small-but-variable number of components are to be connected. Buses can be very efficient if each component desires to communicate rarely but to have messages travel at speed, or when many receivers want access to the same message.

Buses are also roughly the topology that a wireless network naturally takes — radio signals are received by all receivers within range of the transmitter, and two simultaneous transmitters will likely collide. In practice, wireless networks are not quite modeled by the bus topology because, for example, two transmitters can be in range of one receiver but not of each other (called the hidden terminal problem).

3 The Bus

Inside a computer’s casing, it is common to have several special-purpose networks to connect various components of the system. Because early implementations had a bus topology, these are all commonly called buses, and in many cases referred to simply as the bus.

3.1 The system bus

In historical processor designs, the system bus, also known as the front-side bus, connects the processor with memory, I/O devices, and other processors. In a typical implementation, though this bus is a single channel, it is not a single wire connecting components but a collection of wires, some dedicated to the addresses and some dedicated to the data. There will be enough address wires so that an entire address can be specified all at once (for example, on the Intel 80386, using 30 binary wires to specify a 30-bit address) and usually enough data wires to transfer at least a byte of data at a time (on the Intel 80386, up to 32 bits at a time using 32 binary wires).

In addition to wires for data and addresses, there will be wires dedicated to controlling which device uses the shared bus and preventing conflicts.

Components like memory, graphics cards, I/O devices, etc. were generally not connected directly to the system bus. Instead, intermediate chips would translate from the processor bus to other types of buses. In the Intel design, there were originally two of these chips called the Memory Controller Hub or Northbrige (for memory and higher-speed devices) and the I/O Controller Hub or Southbridge (for lower-speed devices). These chips would often use a bus topology to communicate with their devices.

3.2 Modern processors and buses

More recent processors have tended to move some of the functionality that was typically on these intermediate chips to the main processor package. In addition, processor manufacturers prioritized making multi-core systems more efficient, and the bus topology does not work well to connect many cores.

The design that AMD and Intel seem to have settled on in the current generation1 generally has the processor package feature separate buses for communicating with memory and for communicating with I/O devices or other processor packages. Within a processor package, there are generally internal networks that connect cores, caches, memory bus controllers, and other components. Since the design of these internal networks can change without the involvement of motherboard manufacturers and the like, processor manufacturers have more flexibility to change the design of these networks.

3.3 Memory and I/O buses

Connecting the processor to memory and I/O devices is often done through various other buses:

  1. as of 2022↩︎

  2. as of 2022↩︎

  3. This stands for peripheral component interconnect but is almost universally called by its acronym, so much so that I’d expect that using the full name would confuse people.↩︎

  4. as of 2019↩︎

  5. ATA stands for AT Attachment. AT is short for IBM Personal Computer AT, the product which popularized this attachment technology. In that computer’s name, AT stood for advanced technology.↩︎