This page is for a prior offering of CS 3330. It is not up-to-date.
This page contains quizzes given Fall 2015. For other semesters see the main old quizzes page
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Our textbook and most GNU tools using ATT format assembly, but 2150 uses Intel format assembly instead. Each of the following is either true for ATT or Intel format, but not both; which are true of ATT format assembly? Select all that apply.
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The textbook shows two ways to translate a while loop to use goto statements: jump to middle and guarded do. Optimizing compilers prefers guarded do. This is because
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The call instruction changes which of the following registers? Select all that apply.
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Most jumps can only go to compile-time-known addresses, but the C switch command jumps to a runtime-computed address using jmp *label(offset) syntax x86-64 assembly. Which Y86-64 command moves the program counter to a runtime-computed address?
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Which of the following Y86-64 assembly snippets does the same thing as cmovle %rbx, %rax? |
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The C operators & and && function differently in that both (1) & is bit-wise but && is logical instead; and (2) && short-circuits, only evaluating the second operand if the first operand was true. The AND gates and HCL && operator described in the book
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The C operators & and && function differently in that both (1) & is bit-wise but && is logical instead; and (2) && short-circuits, only evaluating the second operand if the first operand was true. The AND gates and HCL && operator described in the book
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Supposed I have a register and want to be able to stallit, preventing it from storing new values when there is a 0 on wire X. While the register is stalled, I want it to keep whatever value it had when I stalled it until X has a 1 again, at which point it may resume normal operation. To do this, I should |
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Supposed I have a register and want to be able to bubbleit, such that if there is a 0 on wire X then it outputs a 0 no matter what its data input is. To do this, I should |
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jprto SEQ that jumps to a program register. A use of the instruction might look like jpr %rdi
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Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a single-instruction program run faster?
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Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a 50-instruction program run faster?
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Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will
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Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will
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bubbleand stallmean different things when applied to register (like R1) vs stages (like S1). |
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Which of the following is likely to increase the cache-friendliness of code the most?
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Which of the following terms is a general term that includes the others as sub-kinds?
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Let C be the set of all possible concurrent processes and P be the set of all possible parallel processes.
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Most processors contain a special one-bit register called the mode bitthat distinguishes between kernel mode and user mode. True or false: when in user mode, programs can run some but not all of the assembly instructions they can run in kernel mode. |
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True or false: when in user mode, programs can access some but not all of the addresses that they can access in kernel mode.
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True or false: when in user mode, programs can access some but not all of the file system locations that they can access in kernel mode.
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Select all that apply:
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(select all that apply) A PTE describes where a particular range of addresses in virtual memory is stored. It can be
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A PTE describes where a particular range of addresses in virtual memory is stored, as well as all but one of the following; which one is not part of PTE?
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For multi-level page tables, each process has several page tables for its memory. What is the size of each of these page tables?
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Compare and contrast memory caching (where slow RAM and fast L# caches interact to provide the illusion of a large, fast memory) and virtual memory (where slow disk and fast RAM interact to provide the illusion of large, fast memory). Several questions refer to The table below summarizes the paragraph above:
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