CS 6354: Graduate Computer Architecture

1 Homework 1

Checkpoint: due 12 September 2016 11:59PM

Due: due 23 September 2016 11:59PM 26 September 2016 11:59 AM

The design of memory hierarchies has a very large effect on application performance. In tuning a memory hierarchy, architects have a large number of parameters, including the sizes of each level of cache, the layout (associativity) of each level of cache, prefetching policies, how caches are distributed between cores, etc. If these decisions have a substantial effect on application performance, they ought to be observable from applications. Your assignment is to produce microbenchmarks that will reveal many of these parameters.

Choose a system you have access to. Construct microbenchmarks from whose results one should be able to infer its value (time, size, or whether a feature exists) of each of the following:

For checkpoint:

For final submission:

and at least two of:

You are encouraged to observe performance counters, such as numbers of last-level cache misses, that may directly reflect cache accesses and other memory system activity you are trying to benchmark. If practical, however, your benchmark should reveal the parameter based on performance alone.

Note that due to features of modern processors, you may not be able to obtain reasonable results for some measurements despite substantial effort that would not be necessary on some platforms. In this case, I do not want to punish you for choosing a more interesting microarchitecture; instead, please document what you tried and what the negative results were.

You may read the value of the parameters manually from your benchmark results (for example, based on the shape of the graph) instead of automating this process (but it would be awesome if you did automate it).

2 Deliverables

A single zip or tar archive containing:

3 Report

A document in PDF, HTML, or text format:

4 Notes

5 References that might be useful