Ashish Venkat

Associate Professor
Department of Computer Science
University of Virginia
Office: Rice 312
Email: <lastname>@virginia.edu

My research interests lie broadly in Computer Architecture, Compilers, and Computer Security. My research explores novel and cross-disciplinary hardware and software techniques to design secure systems that offer robust exploit mitigations, while maintaining high levels of performance, energy efficiency, and programmability. I'm also interested in applying novel machine learning techniques to detect and mitigate security threats, model dynamic execution behavior, and provide efficient hardware/runtime support to enable the seamless adoption of highly heterogeneous platforms and emerging computing paradigms.

I am looking for motivated graduate students who are interested in the general area of Computer Architecture, Compilers, and Security.

News

2025

  • Honored to have been recognized at UVA's university-wide Sixth Annual Research Achievement Awards through a nomination from the Dean of Engineering for making substantial contributions to the field of study, influencing the academic community, or having a positive impact on society.

    • 2024

  • Our paper on Ceviche, a novel capability-based secure cache design has been accepted to IEEE Security and Privacy (S&P 2025), at an acceptance rate of 14%!
  • Our paper on securing large monolithic and heterogeneous systems has been accepted to the Special Session on Security-By-Design at the Embedded Systems Week with visioning talks from research groups headed by Todd Austin, Guru Venkataramani, Sai Manoj Pudukotai, and myself.
  • Our paper on modeling and benchmarking for digital PIM architectures has been accepted to IISWC 2024.
  • We received a DARPA award on HERCULES: Hardware-Enhanced Resilient Compartmentalization and Program Analysis for Upgraded Legacy Environment Security. The total award amount is $4.9 million dollars with UVA as the prime (myself as the PI and Jack Davidson as the co-PI), in collaboration with UC Riverside and UC Irvine as subcontractors. Thanks to DARPA for the generous funding!
  • Honored to have been recognized for outstanding research and scholarship at UVA's university-wide Fifth Annual Research Achievement Awards (National Recognition Category).

    • 2023

  • My student Lingxi Wu (co-advised with Kevin Skadron) successfully defended his Ph.D. dissertation. He will be joining Open Sesame as an architect.
  • My student Uday Kiran successfully obtained his Master's degree in Computer Science. He will be joining AMD as a Staff Engineer.
  • Honored to have appeared in the list of prolific authors at ISCA for the decade 2013-2022, put together as part of the retrospective on Fifty Years of ISCA! Thanks to my amazing co-authors, who I have been fortunate to collaborate with!
  • Our paper on leveraging processing-with-storage-technology (PWST) to accelerate k-mer counting has been accepted to appear in the ACM Transactions on Architecture and Code Optimization journal (ACM TACO).
  • My student Alenkruth Krishnan Murali's paper on Core Fuzzing has been accepted to SRC TECHCON 2023!
  • My students Lingxi Wu and Rahul Sreekumar put together an amazing set of presentation materials (Slides, Video, Poster) describing our DATE 2023 work on New Hardware Trojans in Neuromorphic Architectures that has been nominated for the Best Paper Award!
  • Received the prestigious NSF CAREER award! Thanks to NSF for the generous support!

    • 2022

  • My student Conner Ward successfully defended his Master's thesis on Speculative Vector Widening! Congratulations to Conner!
  • Our paper on Hardware Trojan threats in eNVM devices has been accepted to DATE 2023, and has been nominated for Best Paper Award!
  • My student Logan Moody gave an excellent talk on our work on Speculative Code Compaction in Chicago, at MICRO 2022.
  • Our MICRO 2022 paper has been awarded all three artifact badges (Available, Functional, Reproduced)! Our codebase is now available on GitHub!
  • I have been invited to participate in CRA's Computing Community Consortium (CCC) visioning workshop on Mechanism Design for Improving Hardware Security organized by Simha Sethumadhavan and Tim Sherwood! Thanks for the extremely invigorating brainstorming sessions!
  • Our paper on DRAM-CAM, an architecture for General-Purpose Bit-Serial Exact Pattern Matching, has been accepted to IEEE Computer Architecture Letters
  • Our paper on Speculative Code Compaction (SCC) has been accepted to appear in MICRO 2022!. SCC is an aggressive microarchitectural optimization that is able to leverage speculatively identified program invariants to accelerate inherently sequential and statically compile-time optimized code, without the need for profiling, compiler metadata, or other source-level information.
  • We have been awarded a large NSF PPoSS grant to pursue research on co-designing Hardware, Software, and Algorithms to Enable Extreme-Scale Machine Learning Systems. Thanks to NSF for the generous support!
  • Our paper on ProxyVM, a privacy-preserving machine learning framework, has been accepted at SRC TECHCON 2022!
  • We have been awarded an NSF CCRI grant to pursue research on a scalable Hardware and Software Environment Enabling Secure Multi-party Learning. Thanks to NSF for the generous support!

    • 2021

  • SRC contract awarded for our work on privacy-preserving machine learning, with Intel Labs and IBM Research as our industry liaisons. Thanks to SRC, Intel, and IBM for the generous support!
  • Our paper on CHEx86, a transparent and high performance memory safety solution, has been recognized as a 2021 Top Pick in Hardware and Embedded Security, among hardware security conference papers that have appeared in the last 6 years (2015-2020) in leading architecture, security, and VLSI design conferences.
  • Our USENIX Security 2022 paper has been awarded all three artifact badges (Available, Functional, Reproduced)! Our codebase is now available on GitHub!
  • Our paper on secure SMT architectures got accepted to USENIX Security 2022!
  • Our proof-of-concept exploit code for our transient execution attack variants that exploit the micro-op cache is now available on Github.
  • My students, Xida Ren, Logan Moody, and Lingxi Wu, put together excellent video presentations (links below) for the upcoming ISCA 2021 global virtual conference.
  • Our work on the micro-op cache vulnerability has been covered widely by a number of global technology news and mainstream media outlets!
  • Our group shines again at the 2021 Annual Computer Science Department Awards Ceremony! Congratulations to Xida Ren for winning the Graduate Service Award and to Joey Rudek for winning the Louis T. Rader Undergraduate Teaching Award!
  • My students, Xida Ren and Logan Moody, gave an excellent talk at Intel labs on their recent ISCA work -- I See Dead µops, a novel transient execution attack that exploits Intel/AMD µop caches to leak secrets.
  • Two papers accepted to ISCA 2021!

    • 2020

  • Our Spectre mitigation paper on Context-Sensitive Fencing has been selected as a 2020 Top Pick in Hardware and Embedded Security, among hardware security conference papers that have appeared in the last 6 years (2014-2019) in leading architecture, security, and VLSI design conferences.
  • My student, Layne Berry, presented our work on speculative superoptimization at SRC TECHCON 2020.
  • Our research on Composite-ISA Cores has been covered by Coreteks, in the article "AMD Master Plan Pt. 2 -- Heterogeneous Revolution"!
  • Received an NSF REU supplement award to our FoMR grant to support undergraduate research. Thanks to NSF for the generous support!
  • I gave a virtual tech talk to Intel Labs and the FoMR community, on our work on superoptimization.
  • My student, Rasool Sharifi, gave an excellent talk about our work on CHEx86 at ISCA 2020!
  • Our research group shines at the 2020 Annual Computer Science Department Awards Ceremony! Congratulations to Layne Berry for winning two awards -- the Louis T. Rader Undergraduate Research Award and the Louis T. Rader Outstanding Undergraduate Student Education Award! Congratulations to Ishika Paul for winning the Outstanding Graduate Student Teaching Award!
  • Paper on CHEx86, a microcode-based capability machine accepted to ISCA 2020!
  • Paper on the Packet Chasing attack accepted to ISCA 2020!
  • I'm serving as the Student Travel Grant Chair for HPCA 2020. I have been awarded an NSF grant to support student travel to the conference. Thanks to NSF for the generous support!

    • 2019

  • Congratulations to my student, Layne Berry, who has been recognized nationally as one of CRA's Outstanding Undergraduate Researcher Award Honorable Mention recipients!
  • I will be providing teaching mentorship to my student, Ishika Paul, under the Engineering Graduate Teaching Internship (GTI) program in Spring 2020.
  • Presented our work on microcode customization at University of Cambridge, UK.
  • Attending the NSF SaTC 2019 PI Meeting at Alexandria, VA.
  • We expose yet another new vulnerability in Intel CPUs, in our paper on Packet Chasing -- verfied by Intel (CVE-2019-11184)!
  • NSF/Intel FoMR Grant awarded: Speculative Superoptimization -- Boosting Performance via Speculation-Driven Dynamic Binary Optimization. Thanks to NSF and Intel for their generous support!
  • Paper on ML-based scheduling accepted at SAMOS 2019!
  • My first mentee, Kazem Taram, gave an amazing talk about our Spectre mitigation, Context-Sensitive Fencing, at ASPLOS 2019!
  • Presented our work on Heterogeneous-ISA architectures at NC State University.
  • Composite-ISA Cores recognized as the best paper runner-up at HPCA 2019!
  • Presented our work on Composite-ISA Cores at HPCA 2019.
  • Our work on Microcode Customization has been recognized as an IEEE Micro Top Pick of all Computer Architecture conferences held in 2019!

    • 2018

  • NSF SaTC CRII Grant awarded: Mitigating Microarchitectural Attacks via Microcode Customization!. Thanks to NSF for the generous support!
  • Paper on Spectre mitigation accepted to ASPLOS 2019!
  • Paper on Composite-ISA Cores accepted to HPCA 2019!
  • DARPA SSITH subcontract awarded for our microcode customization work. Thanks to DARPA for their generous support!
  • Presented our Spectre defense work at Intel Labs, Santa Clara.
  • Joined the CS Department at UVA as Tenure-track Assistant Professor!

    • Students

    I am very fortunate to work with an outstanding group of graduate and undergraduate students.

    Graduate Students

    Logan Moody
    Arnabjyoti Kalita
    Alenkruth Krishnan Murali
    Saket Upadhyay
    Yilong Yang

    Undergraduate Students

    Sam Colvin
    Griffin Chozick
    Alex Schaefer
    Amanda Hail
    Lars Christensen

    Alumni

    Lingxi Wu, Ph.D. 2023 (co-advised with Kevin Skadron), now at Black Sesame
    Uday Kiran, MS 2023, now at AMD
    Wei Qi, MS 2022, now pursing Ph.D. in Cryptography at Università Bocconi
    Conner Ward, MS 2022
    Muhammad Abdullah, BACS 2022, now pursuing Law at Columbia Law School
    Layne Berry, BACS 2021, now pursuing Ph.D. at University of Texas, Austin
    Joey Rudek, BACS 2021, now pursuing Ph.D. at University of California, San Diego

    Papers

    Ceviche: Capability-Enhanced Virtualization of Caches

    Arnabjyoti Kalita, Yilong Yang, Alenkruth Krishnan Murali, Ashish Venkat,
    In Proceedings of the 46th IEEE Symposium on Security and Privacy (S&P), May, 2025.
    [ Slides ] [ Acceptance rate: 14% ]

    Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions

    Venkat Nitin Patnala, Sai Manoj Pudukotai Dinakarrao, Guru Venkataramani, Jie Chen, Milos Doroslovacki, Fan Yao, Hongyu Fang, Meron Demissie, Todd Austin, Lauren Biernacki, Saket Upadhyay, Arnabjyoti Kalita, Ashish Venkat,
    In Proceedings of the 2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September, 2024.
    [ Slides ] [ Acceptance rate: 28% ]     Special Session Article!

    Tools-Architectural Modeling and Benchmarking for Digital DRAM PIM

    Farzana Siddique, Deyuan Guo, Zhenxing Fan, Mohammadhosein Gholamrezaei, Khyati Kiyawat, Morteza Baradaran, Alif Ahmed, Kyle Durrer, Abdullah T. Mughrabi, Hugo Abbot, Ethan Ermovick, Ashish Venkat, Kevin Skadron,
    In Proceedings of the 2024 IEEE International Symposium on Workload Characterization (IISWC), September, 2024.
    [ Slides ] [ Acceptance rate: 40% ]

    Hardware Trojan Threats in eNVM Neuromorphic Devices

    Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Mircea Stan, Ashish Venkat,
    In Proceedings of the 26th Design, Automation and Test in Europe Conference (DATE), April, 2023.
    [ Slides | Poster | Video] [ Acceptance rate: 25% ]     Nominated for Best Paper Award!

    Abakus: Accelerating k-mer Counting With Storage Technology

    Lingxi Wu, Minxuan Zhou, Weihong Xu, Ashish Venkat, Tajana Rosing, Kevin Skadron
    In ACM Transactions on Architecture and Code Optimization (ACM TACO), November, 2023. [ Impact Factor: 1.6 ]

    Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations

    Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat,
    In Proceedings of the 55th ACM/IEEE International Symposium on Microarchitecture (MICRO), October, 2022.
    [ Slides | Software Artifact ] [ Acceptance rate: 23% ]

    ProxyVM: A Scalable and Retargetable Compiler Framework for Privacy-Aware Proxy Workload Generation

    Xida Ren, Alif Ahmed, Yizhou Wei, Kevin Skadron, Ashish Venkat,
    In Semiconductor Research Corporation's Annual Technical Conference (SRC TECHCON), September, 2022.

    DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching

    Lingxi Wu, Rasool Sharifi, Ashish Venkat, Kevin Skadron,
    In IEEE Computer Architecture Letters (IEEE CAL), Issue 2, Jul-Dec, 2022.

    SecSMT: Securing SMT Processors against Contention-Based Covert Channels

    Mohammadkazem Taram, Xida Ren, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 31st USENIX Security Symposium (USENIX Security), Aug, 2022.
    [ Software Artifact ] [ Acceptance rate: 17% ]

    I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches

    Xida Ren, Logan Moody, Mohammadkazem Taram, Matthew Jordan, Dean M. Tullsen, Ashish Venkat,
    In Proceedings of the 48th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2021.
    [ Video | Proof-of-Concept Exploit Code ] [ Acceptance rate: 18% ]

    Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching

    Lingxi Wu, Rasool Sharifi, Marzieh Lenjani, Kevin Skadron, Ashish Venkat,
    In Proceedings of the 48th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2021.
    [ Video ] [ Acceptance rate: 18% ]

    CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities

    Rasool Sharifi and Ashish Venkat,
    In Proceedings of the 47th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2020.
    [ Video ] [ Acceptance rate: 18% ]     IEEE Design & Test Top Pick for architecture/security/VLSI design conferences held between 2015-2020!

    Packet Chasing: Spying on Network Packets over a Cache Side-Channel

    Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 47th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2020.
    [ Video ] [ Acceptance rate: 18% ]

    Platform-Agnostic Learning-Based Scheduling

    Andreas Prodromou, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019.

    Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management

    Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen,
    In IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences (IEEE Micro Top Picks), May, 2019. [ Acceptance rate: 9% ] Theme Article!

    Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization

    Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April, 2019.
    [ Slides ] [ Acceptance rate: 21% ]     IEEE Design & Test Top Pick for architecture/security/VLSI design conferences held between 2014-2019!

    Fast and Efficient Deployment of Security Defenses via Context Sensitive Decoding

    Mohammadkazem Taram, Dean M. Tullsen, Ashish Venkat, Houman Homayoun, Sai Manoj MD,
    In Proceedings of the 44th Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March, 2019.

    Composite-ISA Cores: Enabling Multi-ISA Heterogeneity using a Single ISA

    Ashish Venkat, Harsha Basavaraj, Dean M. Tullsen,
    In Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA), February, 2019.
    [ Slides ] [ Acceptance rate: 21% ]     Best Paper Award Runner-Up!

    Deciphering Predictive Schedulers for Heterogeneous-ISA Architectures

    Andreas Prodromou, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), Feburary, 2019.

    Breaking the ISA Barrier in Modern Computing

    Ashish Venkat,
    Doctoral Dissertation, UC San Diego, July, 2018.

    Mobilizing the Micro-Ops: Exploiting Context-Sensitive Decoding for Security and Energy Efficiency

    Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2018.
    [ Slides ] [ Acceptance rate: 17% ]     IEEE Micro Top Pick for architecture conferences held in 2018!

    Reliability-Aware Data Placement for Heterogeneous Memory Architecture

    Manish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean Tullsen, Rajesh Gupta,
    In Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA), February, 2018.
    [ Slides ] [ Acceptance rate: 21% ]

    HIPStR: Heterogeneous-ISA Program State Relocation

    Ashish Venkat, Sriskanda Shamasunder, Hovav Shacham, Dean M. Tullsen,
    In Proceedings of the 21st ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April, 2016.
    [ Slides | Poster ] [ Acceptance rate: 22% ]

    Binary Translator driven Program State Relocation

    Ashish Venkat, Arvind Krishnaswamy, Koichi Yamada, Rajan Palanivel,
    United States Patent Grant US009135435B2, September, 2015

    Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor

    Ashish Venkat and Dean M. Tullsen,
    In Proceedings of the 41st ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2014.
    [ Slides ] [ Acceptance rate: 18% ]

    Execution Migration in a Heterogeneous-ISA Chip Multiprocessor

    Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen,
    In Proceedings of the 17th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March, 2012.
    [ Slides ] [ Acceptance rate: 21% ]

    Teaching

    CS 6501/4501: Hardware Security, Fall 2018, Fall 2020, Spring 2023, Spring 2024.
    CS 6354: Graduate Computer Architecture, Fall 2019, Fall 2021, Fall 2022.
    CS 3330: Undergraduate Computer Architecture, Spring 2019, Spring 2020, Spring 2021, Spring 2022.
    CS 4330: Advanced Computer Architecture, Spring 2025.

    Bio

    Ashish Venkat is an Assistant Professor in the Department of Computer Science at the University of Virginia, where he joined after obtaining a Ph.D. from UC San Diego. His research interests are in computer architecture and compilers, especially in instruction set design, processor microarchitecture, binary translation, code generation, and their intersection with computer security and machine learning. He is the recipient of NSF’s prestigious CAREER and CRII awards. His work has been published at top-tier venues such as ISCA, MICRO, ASPLOS, HPCA, IEEE Security and Privacy, and USENIX Security, and has received funding from NSF, DARPA, SRC, and Intel. His work has been recognized as an IEEE Micro Top Pick among all top-tier Computer Architecture Conference papers published in 2019, IEEE Design & Test Top Pick (twice) among all Hardware and Embedded Security papers published in Computer Architecture, Computer Security, and VLSI CAD conferences held in the last six years (in 2020 and 2021), best paper nominee at DATE 2023, and as the runner-up of the HPCA Best Paper Award in 2019. His dissertation research has been successfully ported and transferred to the Cloud Platforms division of the IBM Haifa Research Lab.