• Semester preview: Layers of abstraction
• Processor Fetch Loop
• Endianness

• AT&T syntax assembly
• LEA

in the PM lecture, I made an error in annotating the third option of while exercise; the correct replacement for the jge instruction should be jle, not jg

• LEA
• (briefly) X86-64 calling convention
• If and loops to assembly
• X86 condition codes
  • cmpq versus subq
  • testq %rax, %rax
  • SF, ZF
• Jump Tables

• Jump Tables
• Program Memory Layout (Stack, Heap, etc.)
• Compilation Steps and Object Files
• (briefly) C types
• Pointer Arithmetic
• Aside on undefined behavior
  • Supplementary reading: Regehr, “A Guide to Undefined Behavior in C and C++”

• Bit shifting
• Bitwise and/or/xor
• Idea of bit masks

• Bit puzzle strategies
  • Divide-and-conquer for ?:
  • Parallelism example: any-bit-set with &
• ISAs
• RISC v CISC (start)

• RISC v CISC (finish)
• Y86-64
• using YAS
• Y86 encoding/decoding

• lab postmortem
• Y86 decoding (finish)
• describing hardware and HCLRS
  • wires
  • registers
  • memory, reading
• nop CPU

• MUXes
• nop+halt CPU
• interlude: using HCLRS
• interlude: HCLRS versus the book
• addq CPU

• ALUs
• memory, writing
• mov to register CPU
• mov CPU, complete
• SEQ “stages”

There were some technical difficulties (that is, my internet disconnected) during the PM lecture. I believe I’ve cut together a video that omits them in the (non-Zoom) recording linked here, but you might prefer to use the last 7 minutes or so of the AM lecture instead of the rushed coverage of that material in the PM lecture.

• SEQ stages walkthrough
• (briefly) setting MUXes
• pipelining idea (laundry example)

Correction to lecture: In the AM lecture (only), I wrote “1”, “2” and “3” (to label where each instruction was) in the wrong order (not matching the assembly or the question) on the processor diagram (3 was drawn over the writeback stage, even though the question was about instruction 1 being in the writeback stage). Then, when explaining the exercise, I looked at the numbers I drew and said “instruction 3” when I really meant “instruction 1” and vice-versa.

• latency and throughput and pipelining
• register tolerances and diminishing pipelining returns
• pipelined addq
• pipelining SEQ

• data hazards
• stalling
• forwarding

• forwarding paths exercise
• alternate pipelines?
• basic branch prediction and squashing
• implementing stalling and squashing (start)

• implementing stalling and squashing (finish)
• missing pieces in pipelining
• place of cache
• direct-mapped caches (start)

• direct-mapped caches
• set-associative caches (start)

There were some technical difficulties in the AM lecture, so you might prefer the PM recording.

• set-associative caches (finish)
  • tag/index/offset exercise
• replacement policies
• classifying misses: conflict / capacity / compulsory
• cache write policies
• AMAT (AM only)

• AMAT (PM only)
• cache tradeoffs
• cache misses and C code (start)

• cache misses and C code (finish)
• cache blocking
  • supplementary reference: Goto and van de Geijn, “Anatomy of a High Performance Matrix-Multiply”

• cache blocking (finish)
• inlining
• loop unrolling
• out-of-order processor model (start)
  • register renaming

• out-of-order processor model (finish)
  • instruction dispatch
• data flow model
• reassociation
• multiple accumulators
• aliasing (start)

• aliasing (finish)
• inlining
• SIMD

• SIMD (finish)
• processes and context switching
• types of exceptions
• process idea
• (am) exception tables

• exception tables
• kernel mode
• “toy” page table
• address space sizes and splitting addresses

• storing page tables in memory
• page table tricks
  • swapping (physical memory as a cache for disk)
• multi-level page tables (start)

• multi-level page tables (finish)
• multi-level page table access exercises
• TLBs, briefly

• notes: am; pm

Final released noon (Eastern time) 10 December

Final due noon (Eastern time) 11 December