• Semester preview: Layers of abstraction
• Processor + Memory Fetch Loop
• Endianness
• (start) AT&T syntax assembly

• AT&T syntax assembly
• LEA
• labels

• (briefly) X86-64 calling convention
• If and loops to assembly
• X86 condition codes
  • cmpq versus subq
  • testq %rax, %rax
  • SF, ZF
• (briefly) Jump Tables

Due to technical difficulties the 5pm lecture video is incomplete: the screencapture for the first 27 minutes was not recorded, I’ve replaced it with a static shot of the slides that were being displayed, but without the pointer/drawings on those slides.

• Program Memory Layout (Stack, Heap, etc.)
• Compilation steps and object files
• (briefly) C types
• pointer arithmetic and arrays
• Aside on undefined behavior
  • Supplementary reading: Regehr, “A Guide to Undefined Behavior in C and C++”

• Bit shifting
• Bitwise and/or/xor
• Idea of bit masks
• Bit puzzle strategies (start)
  • Divide-and-conquer example: ?:

• Bit puzzle strategies (con’t)
  • Parallelism example: any-bit-set with &
• ISAs
• RISC v CISC

• Y86-64
• using YAS
• Y86 encoding/decoding
• describing hardware and HCLRS
  • wires

• describing hardware and HCLRS (con’t)
  • wires
  • registers
  • memory, reading
• nop CPU
• MUXes
• nop+halt CPU (start)
  • extracting parts of instructions

• nop+halt CPU (con’t)
  • extracting parts of instructions (reprise)
• interlude: using HCLRS
• interlude: HCLRS versus the book
• addq CPU
• ALUs
• memory, writing
• mov to register CPU

• mov CPU, complete
• SEQ “stages”

• SEQ stages walkthrough (finish)

• setting MUXes

• pipelining idea
  • latency and throughput and pipelining

• latency and throughput and pipelining (review)
• adding pipelines to circuits
• register tolerances and diminishing pipelining returns
• pipelined addq
• pipelining SEQ

• data hazards
• stalling
• forwarding

• forwarding paths exercise
• alternate pipelines?
• basic branch prediction and squashing
• implementing stalling and squashing (start)

• implementing stalling and squashing
• missing pieces in pipelining
• place of cache

• direct-mapped caches
• set-associative caches (start)

• set-associative caches (finish)
• replacement policies
• classifying misses: conflict / capacity / compulsory
• cache write policies

• AMAT
• cache tradeoffs
• cache misses and C code (start)

• cache misses and C code (finish)
• loop orders
• cache blocking (start)
  • supplementary reference: Goto and van de Geijn, “Anatomy of a High Performance Matrix-Multiply”

• cache blocking (finish)
  • supplementary reference: Goto and van de Geijn, “Anatomy of a High Performance Matrix-Multiply”
• loop unrolling
• out-of-order processor model (start)

• out-of-order processor model (finish)
  • register renaming
  • instruction dispatch
• reassociation
• multiple accumulators
• data flow model

• data flow model (con’t)
• aliasing
• inlining

• misc optimizations
• SIMD / vector instructions

• profilers (briefly)

• processes and context switching
• types of exceptions
• process idea
• exception tables

• kernel mode

• “toy” page table

• address space sizes and splitting addresses
• storing page tables in memory

• page table tricks
  • allocate-on-demand
• multi-level page tables
• multi-level page table access exercises (start)

• multi-level page table access exercises (con’t)
• TLBs

• notes: from AM
• notes: from PM
• reference sheet that will be supplied on the final