Due to technical issues, the quality of the audio recording is poor (probably still usable, but not as good as it should be). (last semester’s first lectures cover similar technical material and have recordings available, too.)

• Semester preview: Layers of abstraction
• Processor + Memory Fetch Loop
• Endianness

The video for the first ~hour of the lecture is reconstructed from the slides and so may be a little out of sync. Sorry for the inconvenience. You might also look at last semester’s recording.

• AT&T syntax assembly
• (briefly) X86-64 calling convention
• labels

• LEA
• X86 condition codes
  • cmpq versus subq
  • testq %rax, %rax
  • SF, ZF
• If and loops to assembly
• (briefly) Jump Tables

• Program Memory Layout (Stack, Heap, etc.)
• Compilation steps and object files

• pointer arithmetic and arrays
• Aside on undefined behavior
  • Supplementary reading: Regehr, “A Guide to Undefined Behavior in C and C++”
• Bit shifting

• Bitwise and/or/xor
• Idea of bit masks
• Bit puzzle strategies (start)
  • Divide-and-conquer example: ?:
  • Parallelism example: any-bit-set with &
• ISAs / RISC v CISC (start)

• RISC v CISC / ISAs (finish)
• Y86-64
• using YAS
• Y86 encoding/decoding

• describing hardware and HCLRS
  • wires
  • registers
  • memory, reading
• nop CPU
• MUXes
• nop+halt CPU
  • extracting parts of instructions

• addq CPU

Due to technical issues, only the audio recording of this lecture is available. Please watch the last semester’s lectures instead, part 1 and first half of part 2.

• ALUs
• memory, writing
• mov to register CPU

• mov CPU
• SEQ “stages”
• SEQ stages walkthrough (start)

• SEQ stages walkthrough (finish)

• setting MUXes

• pipelining idea
• latency and throughput and pipelining
• adding pipelines to circuits

• register tolerances and diminishing pipelining returns
• pipelined addq
• critical paths
• pipelining SEQ
• data hazards
• stalling

• forwarding
• forwarding paths exercise
• alternate pipelines?

• Watch today’s video
• data hazards, forwarding
• forwarding paths, control hazard
• basic branch prediction

• branch prediction and squashing
• implementing stalling and squashing
• PC-setting logic for jXX, ret

• place of cache, locality
• direct-mapped caches
  • tag/index/offset
  • access patterns

• set-associative caches
• replacement policies
• cache write policies

• AMAT
• cache tradeoffs
• cache misses and C code (start)

• cache misses and C code (start)
• counting misses approximately
• loop orders
• cache blocking (start)
  • supplementary references:
    • Lam, Rothberg, and Wolf, “The Cache Performance and Optimization of Blocked Algortihms” (ASPLOS’91) — the introduction gives a description of cache blocking (and the rest analyzes the resulting cache performance)
    • Goto and van de Geijn, “Anatomy of a High Performance Matrix-Multiply” — close to state-of-the-art on cache optimizations for matrix multiply, but quite dense

• cache blocking (finish)
• loop unrolling

• out-of-order processor model
  • register renaming
  • instruction dispatch
• data flow model
• reassociation
• multiple accumulators (start)

• multiple accumulators (finish)
• aliasing
• inlining
• misc optimizations

• SIMD / vector instructions
• profilers (briefly)

• processes and context switching
• types of exceptions
• process idea
• exception tables

• kernel mode

• “toy” page table
• permission bits in page tables

note: the first 20 minutes of the video of the lecture recording may be out of sync — it was reconstructed later (due to a technical issue)

• address space sizes and splitting addresses
• storing page tables in memory
• page table in memory access exercise

• TLBs, briefly

• final exam review:

  • notes

2-5pm.

Wilson 301.