• Semester preview: Layers of abstraction
• Processor + Memory Fetch Loop
• Endianness

Due to a technical issue the last half of video recording for the 9:30am lecture is missing. (Sorry for the error.) The audio should still be fine. The 11:30am recording should be complete.

• AT&T syntax assembly
• (briefly) X86-64 calling convention
• labels

• LEA
• X86 condition codes
  • cmpq versus subq
  • testq %rax, %rax
  • SF, ZF
• If and loops to assembly
• (briefly) Jump Tables

• [11am] finish loops-to-asm
• Program Memory Layout (Stack, Heap, etc.)
• Compilation steps and object files
• (briefly) C types
• pointer arithmetic and arrays
• Aside on undefined behavior
  • Supplementary reading: Regehr, “A Guide to Undefined Behavior in C and C++”

• Bit shifting
• Bitwise and/or/xor
• Idea of bit masks
• Bit puzzle strategies (start)
  • Divide-and-conquer example: ?:

• Bit puzzle strategies (con’t)
  • Divide-and-conquer example: ?: (finish)
  • Parallelism example: any-bit-set with &
• ISAs
• RISC v CISC

• Y86-64
• using YAS
• Y86 encoding/decoding
• describing hardware and HCLRS (start)

• describing hardware and HCLRS (con’t)
  • wires
  • registers
  • memory, reading
• nop CPU
• MUXes
• nop+halt CPU
  • extracting parts of instructions

• addq CPU
• ALUs
• memory, writing
• mov to register CPU
• mov CPU

• SEQ “stages”
• SEQ stages walkthrough
• [9am] setting MUXes

• setting MUXes (finish)

• pipelining idea
• latency and throughput and pipelining
• adding pipelines to circuits
• register tolerances and diminishing pipelining returns
• pipelined addq (start)

• pipelined addq (finish)
• critical paths
• pipelining SEQ
• data hazards
• stalling
• forwarding (start)

• forwarding (finish)
• forwarding paths exercise
• alternate pipelines?

• basic branch prediction and squashing
• implementing stalling and squashing

• PC-setting logic for jXX, ret
• missing pieces in pipelining
• place of cache
• direct-mapped caches (start)
  • tag/index/offset

• direct-mapped caches
  • access patterns
• set-associative caches (start)

• set-associative caches (finish)
• replacement policies
• classifying misses: conflict / capacity / compulsory
• cache write policies
• AMAT (start)

• AMAT (finish)
• cache tradeoffs
• cache misses and C code (start)

• cache misses and C code (finish)
• counting misses approximately
• loop orders

• cache blocking
  • supplementary references:
    • Lam, Rothberg, and Wolf, “The Cache Performance and Optimization of Blocked Algortihms” (ASPLOS’91) — the introduction gives a description of cache blocking (and the rest analyzes the resulting cache performance)
    • Goto and van de Geijn, “Anatomy of a High Performance Matrix-Multiply” — close to state-of-the-art on cache optimizations for matrix multiply, but quite dense
• loop unrolling
• out-of-order processor model (start)

• out-of-order processor model (finish)
  • register renaming
  • instruction dispatch
• data flow model
• reassociation
• multiple accumulators

Due to a technical issue, the screencapture of the 11am lecture is incomplete. Please use the 9:30am one instead.

• aliasing
• inlining
• misc optimizations

• SIMD / vector instructions
• profilers (briefly)

• processes and context switching
• types of exceptions
• process idea
• exception tables

• kernel mode

• “toy” page table

• review “toy” page table
• address space sizes and splitting addresses
• storing page tables in memory

• page table in memory access exercise
• multi-level page tables
• multi-level page table access exercise
• page table tricks, briefly
  • allocate-on-demand + swapping

• notes: 9:30am; 11am