Please further note that any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the sponsoring agencies or employers.

Multi-core and Multi-threading

• Rodinia Benchmarks Wiki

• D. Tarjan, J. Meng, and K. Skadron.  "Increasing Memory Miss Tolerance for SIMD Cores."  In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009, to appear. (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009.  (pdf)

• J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.”  In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)

• D. Tarjan.  "Efficient Throughput Cores for Asymmetric Manycore Processors."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2009. (pdf)

• J. Meng and K. Skadron.  "Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs."  In Proceedings of the 23rd Annual ACM International Conference on Supercomputing (ICS), pp. 256-65, June 2009.  (pdf)

• M. Boyer, D. Tarjan, S. T. Acton, and K. Skadron.  "Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors."  In Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2009.  (pdf)

• J. Meng, D. Tarjan, and K. Skadron. “Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision.” Tech. Report CS-2009-02, Univ. of Virginia Dept. of Computer Science, Apr. 2009. (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron.  "A Performance Study of General Purpose Applications on Graphics Processors using CUDA."  Journal of Parallel and Distributed Computing, Elsevier, online June 2008, DOI http://dx.doi.org/10.1016/j.jpdc.2008.05.014. (UVA final preprint pdf | published pdf)

• S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach. “Accelerating Compute Intensive Applications with GPUs and FPGAs.” In Proceedings of the IEEE Symposium on Application Specific Processors (SASP), pp. 101-07, June 2008.  (pdf)

• D. Tarjan, M. Boyer, and K. Skadron. “Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue.” In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf)

• W. Huang, M. R. Stan, K. Sankaranarayanan, Robert J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective.”  In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008.  (pdf)

• J. Meng, S. Che, J. W. Sheaffer, J. Li, J. Huang and K. Skadron.  "Hierarchical Domain Partitioning For Hierarchical Architectures." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, June 2008. (pdf)

• W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron.  "Many-Core Design from a Thermal Perspective: Extended Analysis and Results." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, Apr. 2008. (pdf)

• J. Nickolls, I. Buck, M. Garland, K. Skadron.  “Scalable Parallel Programming with CUDA.”  ACM Queue, 6(2):40-53, Mar.-Apr. 2008.  DOI 10.1145/1365490.1365500 (pdf)

• D. Tarjan and K. Skadron.  “Multithreading vs. Streaming”  Position paper in Proceedings of the SIGPLAN Workshop on Memory Systems Performance and Correctness, Mar. 2008. (pdf)

• S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach.  "Accelerating Compute Intensive Applications with Accelerators."  Tech. Report CS-2008-04, Univ. of Virginia Dept. of Computer Science, Feb. 2008.

• J. Meng, S. R. Tarapore, S. Che, J. Huang, J. W. Sheaffer, and K. Skadron. "Programming with Relaxed Streams." Tech. Report CS-2007-17, Univ. of Virginia Dept. of Computer Science, Dec. 2007. (pdf)

• D. Tarjan, M. Boyer, and K. Skadron.  "Federation: Out-of-Order Execution using Simple In-Order Cores."  Univ. of Virginia Dept. of Computer Science Tech. Report CS-2007-11, Aug. 2007. (pdf)

• E. Humenay, D. Tarjan, and K. Skadron.  "Impact of Process Variations on Multicore Performance Symmetry."  In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007.  (pdf)

• E. Humenay.  "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.

• Y. Li, K. Skadron, B. C. Lee, and D. Brooks.  “Quantifying Latency and Throughput Compromises in CMP Designs.”  Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)

• Y. Li.  "Physically Constrained Chip Multiprocessor Architecture."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006.  Available in pdf

• E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)

• Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. “Impact of Thermal Constraints on Multi-Core Architectures.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf).

• K. Skadron. “Thermal Challenges in Architecting Multi-Core Chips,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer. In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006.

• Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron.  "CMP Design Space Exploration Subject to Physical Constraints."  In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)

• Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.”  Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005.  Available in pdf

• Y. Li, Z. Hu, D. Brooks, and K. Skadron.  “Performance, Energy and Thermal Considerations for SMT and CMP Architectures: Extended Discussion and Results.”  Tech Report CS-2004-32, Univ. of Virginia Dept. of Computer Science, Nov. 2004.  (Extended version of HPCA-11 paper.)

• Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Evaluating the Thermal Efficiency of SMT and CMP Architectures.”  In the IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, external track, Oct. 2004.  (Also published as IBM TJ Watson Research Report RC23281, July 2004.)  Available in pdf

• Y. Li.  "Understanding the Energy Efficiency of Simultaneous Multithreading."  MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2004.

• K. R. Hirst, J. W. Haskins, Jr., and K. Skadron.  “dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading.” IEE Proceedings on Computers and Digital Techniques, 151(1):43-50, Jan. 2004.  Available in pdf.

• K. R. Hirst, J. W. Haskins Jr., K. Skadron. "dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading: Extended Results." Tech Report CS-2003-18, Univ. of Virginia Dept. of Computer Science, Oct. 2003.

• J.W. Haskins, Jr., K.R. Hirst, and K. Skadron.  "Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Block Multithreading: Extensions, Characterization, and Tradeoffs."  In Proceedings of the 20th IEEE International Performance, Computing, and Communications Conference, pp. 319-28, Apr. 2001. Available in postscript (Abstract)

• J.W. Haskins, Jr. and K. Skadron.  "Differential Multithreading: Recapturing Pipeline Stall Cycles and Enhancing Throughput in Small-Scale Embedded Microprocessors."  In Proc. of the Workshop on Complexity-Effective Design, in conjunction with ISCA-27, June 2000. Available in postscript (Abstract)

Thermal

• HotSpot software home page

• K. Sankaranarayanan.  "Thermal Modeling and Management of Microprocessors."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2009.  Available in pdf. 

• W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan. " Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design."  In Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 1-10, Apr. 2009.  (pdf)

• K. Sankaranarayanan, M. R. Stan, and K. Skadron. “A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level.” Tech. Report CS-2009-04, Univ. of Virginia Dept. of Computer Science, April 2009. (pdf)

• K. Sankaranarayanan, W. Huang, M. R. Stan, H. Haj-Hariri, R. J. Ribando, and K. Skadron. “Granularity of Microprocessor Thermal Management: A Technical Report.” Tech. Report CS-2009-03, Univ. of Virginia Dept. of Computer Science, April 2009. (pdf)

• W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan.  "Accurate, Pre-RTL Temperature-Aware Processor Design Using a Parameterized, Geometric Thermal Model."  IEEE Transactions on Computers, 57(9):1277-88, Sept. 2008, DOI 10.1109/TC.2008.64. (pdf)

• W. Huang, M. R. Stan, K. Sankaranarayanan, Robert J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective.”  In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008.  (pdf) 

• W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron.  "Many-Core Design from a Thermal Perspective: Extended Analysis and Results." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, Apr. 2008. (pdf)

• K. Skadron, P. Bose, K. Ghose, R. Sendag, J. J. Yi, and D. Chiou. "Low-Power Design and Temperature Management." IEEE Micro, 27(6):46-57, Nov.-Dec. 2007. DOI 10.1109/MM.2007.104.  (pdf)

• J. W. Sheaffer.  "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007.  Available in pdf.

• W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron. “An Improved Block-Based Thermal Model in HotSpot-4.0 with Granularity Considerations.” In Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking, in conjunction with the 34th International Symposium on Computer Architecture (ISCA), June 2007. (pdf)

• E. Humenay, D. Tarjan, and K. Skadron.  "Impact of Process Variations on Multicore Performance Symmetry."  In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007.  (pdf)

• W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron.  “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations.”  Tech Report CS-2007-07, Univ. of Virginia Dept. of Computer Science, Feb. 2007. (pdf)

• Z. Lu, W. Huang, M. Stan, K. Skadron, and J. Lach.  “Interconnect Lifetime Prediction for Reliability-Aware Systems.”  IEEE Transactions on VLSI Systems, 15(2):159-72, Feb. 2007.  (pdf)

• W. Huang.  "HotSpot—A Chip and Package Compact Thermal Modeling Methodology for VLSI Design."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.  Available in pdf

• Z. Lu.  "Runtime Management Techniques for Power- and Temperature-aware Computing."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.  Available in pdf.

• E. Humenay.  "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.

• S. W. Chung and K. Skadron.  "A Novel Software Solution for Localized Thermal Problems" In Proceedings of the 4th International Symposium on Parallel and Distributed Processing and Applications (ISPA), Springer-Verlag LNCS, pp. 63-74, Dec. 2006.  (pdf)

• Y. Li, K. Skadron, B. C. Lee, and D. Brooks.  “Quantifying Latency and Throughput Compromises in CMP Designs.”  Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)

• Z. Lu, W. Huang, M. R. Stan, K. Skadron, and J. Lach.  "Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications."  Tech Report CS-2006-23, Univ. of Virginia Dept. of Computer Science, Oct. 2006. (pdf) 

• Y. Li.  "Physically Constrained Chip Multiprocessor Architecture."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006.  Available in pdf

• E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)

• W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, and S. Ghosh. “HotSpot: A Compact Thermal Modeling Method for CMOS VLSI Systems.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(5):501-513, May 2006. (pdf)

• S. W. Chung and K. Skadron. “Using on-Chip Event Counters for High-Resolution, Real-Time Temperature Measurements.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf)

• Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. “Impact of Thermal Constraints on Multi-Core Architectures.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf).

• K. Skadron. “Thermal Challenges in Architecting Multi-Core Chips,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer. In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006.

• S. W. Chung and K. Skadron.  "A Novel Software Solution for Localized Thermal Problems."  Tech Report CS-2006-10, Univ. of Virginia Dept. of Computer Science, Apr. 2006. (pdf)

• E. E. Otto, “Temperature-Aware Operating System Scheduling to Manage the Impact of Thermal Throttling.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2006.  (pdf)

• Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron.  "CMP Design Space Exploration Subject to Physical Constraints."  In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)

• Z. Lu, J. Lach, M. R. Stan, and K. Skadron.  “Improved Thermal Management with Reliability Banking.”  IEEE Micro, 25(6):40-49, Nov./Dec. 2005 special issue on Reliability-Aware Microarchitectures. (pdf)

• W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. “Parameterized Physical Compact Thermal Modeling.” IEEE Transactions on Component Packaging and Manufacturing Technology,  28(4):615-22, Dec. 2005.  (pdf)

• K.-J. Lee, K. Skadron, and W. Huang. “Analytical Model for Sensor Placement on Microprocessors.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 24-27.  (pdf)

• S. Velusamy, W. Huang, J. Lach, M. R. Stan, and K. Skadron. “Monitoring Temperature in FPGA based SoCs.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 634-37.  (pdf)

• E. Humenay, W. Huang, M. R. Stan, and K. Skadron.  “Toward an Architectural Treatment of Parameter Variations.”  Tech Report CS-2005-16, Univ. of Virginia Dept. of Computer Science, Sept. 2005.  (pdf)

• K. Sankaranarayanan, S. Velusamy, M.R. Stan, and K. Skadron.  "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level."  The Journal of Instruction-Level Parallelism, vol. 7, Oct. 2005, http://www.jilp.org/vol7/. (pdf)

• Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. Latch­Mux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005.  (pdf)

• W. Huang, E. Humenay, K. Skadron, and M. R. Stan. “The Need for a Full Chip and Package Thermal Model for Thermally Optimized IC Designs.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 245-50, Aug. 2005.  (pdf)

• Z. Lu, J. Lach, M. Stan, and K. Skadron. “Temperature-Aware Modeling and Banking of IC Lifetime Reliability.” Tech Report CS-2005-10, Univ. of Virginia Dept. of Computer Science, June 2005.

• K. Sankaranarayanan, S. Velusamy, and K. Skadron. “Microarchitectural Floorplanning for Thermal Management: A Technical Report.” Tech Report CS-2005-08, Univ. of Virginia Dept. of Computer Science, May 2005.

• K.-J. Lee, “Microarchitectural Temperature Modeling Using Performance Counters.”   Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005.  (pdf)

• K.-J. Lee and K. Skadron. “Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors.” In Proceedings of the Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with the 2005 International Parallel and Distributed Processing Symposium, Apr. 2005.  Available in pdf  [Presentation slides pdf]

• P. Dadvar, “Security Threats of Power and Thermal Control Intefaces.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005.  (pdf)

• P. Dadvar and K. Skadron.  “Potential Thermal Security Risks.”  In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 21), pp. 229-34, Mar. 2005.  Available in pdf

• J. W. Sheaffer, K. Skadron, and D. P. Luebke.  “Studying Thermal Management for Graphics-Processor Architectures.”  In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2005.  (pdf)

• Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.

• S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for Temperature-Aware Microarchitecture Research.” In the 2005 Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf

• Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.”  Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005.  Available in pdf

• Y. Li, K. Skadron, D. Brooks, M. Hempstead, P. Mauro, and Z. Hu. “Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices.” Tech Report CS-2005-01, Univ. of Virginia Dept. of Computer Science, Feb. 2005.

• S. Velusamy, W. Huang, J. Lach, and K. Skadron. “Monitoring Temperature in FPGA based SoCs.” Tech Report CS-2004-39, Univ. of Virginia Dept. of Computer Science, Dec. 2004.

• Y. Li, Z. Hu, D. Brooks, and K. Skadron.  “Performance, Energy and Thermal Considerations for SMT and CMP Architectures: Extended Discussion and Results.”  Tech Report CS-2004-32, Univ. of Virginia Dept. of Computer Science, Nov. 2004.  (Extended version of HPCA-11 paper.)

• Z. Lu, W. Huang, J. C. Lach, M. R. Stan, and K. Skadron.  “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design.”  In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 327-34, Nov. 2004.  Available in pdf

• Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Evaluating the Thermal Efficiency of SMT and CMP Architectures.”  In the IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, external track, Oct. 2004.  (Also published as IBM TJ Watson Research Report RC23281, July 2004.)  Available in pdf

• W. Huang, M. R. Stan, and K. Skadron.  “Physically-Based Compact Thermal Modeling—Achieving Parameterization and Boundary Condition Independence.”  In Proceedings of the  9th International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2004, pp. 287-92.  Available in pdf

• J. W. Sheaffer, D. P. Luebke, and K. Skadron.  “Temperature-Aware GPU Design.”  SIGGRAPH 2004 poster session, Aug. 2004.  (One of 5 semi-finalists for the SIGGRAPH Student Research Competition out of 53 SRC entries and 118 total posters accepted.)  Available in pdf [associated video, AVI]

• W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan.  “Compact Thermal Modeling for Temperature-Aware Design.”  Tech Report CS-2004-13, Univ. of Virginia Dept. of Computer Science, Apr. 2004.  (Extended version of DAC 2004 paper.)

• W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan.  “Compact Thermal Modeling for Temperature-Aware Design.”  In Proceedings of the 41st ACM/IEEE Design Automation Conference (DAC), pp. 878-883, June 2004. Available in pdf

• K. Skadron.  “The Importance of Computer Architecture in Microprocessor Thermal Design,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer.  In Proceedings of the IEEE/ASME Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2004.

• S. S. Kim.  "Characterizing Thermal Behavior of Pentium-IV with Hyperthreading."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2004.  Available in pdf

• E. Wirth, "Thermal Management in Embedded Systems."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2004.  Available in pdf

• K. Skadron, K. Sankaranarayanan, S. Velusamy, D. Tarjan, M.R. Stan, and W. Huang.  “Temperature-Aware Microarchitecture: Modeling and Implementation.”  ACM Transactions on Architecture and Code Optimization, 1(1):94-125, Mar. 2004.  Available in pdf.

• K. Skadron, M.R. Stan, W. Huang, K. Sankaranarayanan, Z. Lu, and J. Lach.  “The Need for a Computer-Architecture Approach to Thermal Management in Computer Systems.”  In Proceedings of the 5th IEEE International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Micro-systems (EuroSimE), pp. 415-22, May 2004.  (Keynote presentation within session.)  Available in pdf

• K. Skadron.  “Hybrid Architectural Dynamic Thermal Management.”  In Proceedings of the 2004 Design, Automation and Test in Europe (DATE) Conference, pp. 10-15, Feb. 2004.    Available in pdf

• W. Huang, Z. Lu, S. Ghosh, M. Stan, J. Lach, and K. Skadron.  “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis.”  Tech Report CS-2004-07, Univ. of Virginia Dept. of Computer Science, Jan. 2004.

• K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan.  “Temperature-Aware Computer Systems: Opportunities and Challenges.”  IEEE Micro, 23(6):52-61, Nov-Dec. 2003.  (Special issue on “Top Picks from Microarchitecture Conferences” for 2003)

   Available in pdf.

• Z. Lu, M. Stan, J. Lach, and K. Skadron.  “Interconnect Lifetime Prediction for Temperature-Aware Design.”  Tech Report CS-2003-21, Univ. of Virginia Dept. of Computer Science, Nov. 2003

• K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan.  “Temperature-Aware Microarchitecture.”  In Proceedings of the 30th International Symposium on Computer Architecture, pp. 2-13, June 2003. Available in postscript or pdf (Abstract)  [software home page] (Extended version appears as TR CS-2003-08.) (Best student paper!)

• K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan.  “Temperature-Aware Microarchitecture: Extended Discussion and Results.”  University of Virginia Dept. of Computer Science Technical Report CS-2003-08, Apr. 2003.  Available in postscript or pdf (Abstract) [software home page]

• M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, and S. Velusamy.  “HotSpot:  A Dynamic Compact Thermal Model at the Processor-Architecture Level.”  Microelectronics Journal: Circuits and Systems, Elsevier, 34(12):1153-65, Dec. 2003. Available in pdf (Abstract)

• K. Skadron et al.  “HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level”.  In Proceedings of the 2002 International Workshop on THERMal Investigations of ICs and Systems (THERMINIC), pp. 169-72, Oct. 2002.  Available in postscript or pdf (Abstract)

• M. Barcella, W. Huang, M. Stan, and K. Skadron.  “Architecture-Level Compact Thermal R-C Modeling.”  Tech Report CS-2002-20, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract)

• K. Skadron, T. Abdelzaher, and M. Stan.  "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management."  In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 17-28, Feb. 2002.    (Extended version appears as TR CS-2001-27.) Available in postscript or pdf  (Abstract) Erratum

• K. Skadron, T. Abdelzaher, and M.R. Stan.  “Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.”  Tech Report CS-2001-27, Univ. of Virginia Dept. of Computer Science, Nov. 2001.  (Extended version of HPCA-8 paper.)   Available in postscript or pdf (Abstract) Erratum

Power

• HotLeakage software home page

• DelayDVS and ClusterControlWare - software for power management in multi-tier servers

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009.  (pdf)

• J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.”  In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)

• T. Horvath and K. Skadron.  "Multi-mode Energy Management for Multi-tier Server Clusters."  In Proceedings of the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 270-79, Oct. 2008. (pdf | DelayDVS and ClusterControlWare software)

• T. Horvath.  "Energy Management in Real-Time Multi-Tier Internet Services." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2008.  Available in pdf.

• S. W. Chung and K. Skadron.  “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.”  IEEE Transactions on Computers, 57(1):7-24, Jan. 2008, DOI 10.1109/TC.2007.70770. (pdf)

• K. Skadron, P. Bose, K. Ghose, R. Sendag, J. J. Yi, and D. Chiou. "Low-Power Design and Temperature Management." IEEE Micro, 27(6):46-57, Nov.-Dec. 2007. DOI 10.1109/MM.2007.104.  (pdf)

• J. W. Sheaffer.  "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007.  Available in pdf.

• T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” IEEE Transactions on Computers, 56(4):444-58, Apr. 2007.  (pdf)

• T. Horvath, K. Skadron, and T. Abdelzaher. "Enhancing Energy Efficiency in Multi-tier Web Server Clusters via Prioritization."  In Proceedings of the 2007 NSF Next Generation Software Workshop, in conjunction with the IEEE International Parallel and Distributed Processing Symposium, Mar. 2007.  (pdf)

• E. Humenay, D. Tarjan, and K. Skadron.  "Impact of Process Variations on Multicore Performance Symmetry."  In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007.  (pdf)

• Z. Lu.  "Runtime Management Techniques for Power- and Temperature-aware Computing."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.  Available in pdf. 

• E. Humenay.  "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.

• Y. Li, K. Skadron, B. C. Lee, and D. Brooks.  “Quantifying Latency and Throughput Compromises in CMP Designs.”  Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)

• Z. Lu, J. Lach, K. Skadron, and M. R. Stan. “Design and Implementation of an Energy Efficient Multimedia Playback System.” In Proceedings of the 40th Asilomar Conference on Signals, Systems and Computers, Oct. 2006. (pdf)

• M. Co, D. A. B. Weikle, and K. Skadron. "Evaluating Trace Cache Energy Efficiency." ACM Transactions on Architecture and Code Optimization (TACO), 3(4):450-76, Dec. 2006. (Abstract | pdf)

• S. W. Chung and K. Skadron.  "Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction."  In Proceedings of the 11th Asia-Pacific Systems Architecture Conference (ACSAC), Sept. 2006, pp. 24-37. (pdf)

• Y. Li.  "Physically Constrained Chip Multiprocessor Architecture."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006.  Available in pdf

• E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)

• S .W. Chung and K. Skadron. “Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction.” Tech Report CS-2006-03, Univ. of Virginia Dept. of Computer Science, Mar. 2006.  (pdf)

• Z. Lu, Y. Zhang, M. R. Stan, J. Lach, and K. Skadron.  “Procrastinating Voltage Scheduling with Discrete Frequency Sets.”   In Proceedings of the ACM/IEEE/EDAA/EDAC 2006 Design, Automation and Test in Europe Conference (DATE), pp. 456-61, Mar. 2006. (pdf)

• Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron.  "CMP Design Space Exploration Subject to Physical Constraints."  In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)

• V. Narayanan and K. Skadron.  "Architectural/System Design and Optimization," in "CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems," E. Macii ed. IEEE Council on Electronic Design Automation (C-EDA) Technology Survey, Jan. 2006.  (IEEE Xplore link)

• Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. Latch­Mux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005.  (pdf)

• Y. Zhang, Z. Lu, M. R. Stan, J. Lach, and K. Skadron. “Optimal Procrastinating Voltage Scheduling for Hard Real-Time Systems.” In Proceedings of the ACM/IEEE 42nd Design Automation Conference (DAC), pp. 905-08, June 2005.  (pdf)

• D. McWhorter, “Power Consumption Characterization of a Graphics Processing Unit.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)

• Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.

• Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.”  Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005.  Available in pdf

• Y. Li, K. Skadron, D. Brooks, M. Hempstead, P. Mauro, and Z. Hu. “Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices.” Tech Report CS-2005-01, Univ. of Virginia Dept. of Computer Science, Feb. 2005.

• T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” Tech Report CS-2004-34, Univ. of Virginia Dept. of Computer Science, Nov. 2004.

• J. C. Lach, J. M. Brandon, and K. Skadron.  “A General Post-Processing Approach to Leakage Current Reduction in SRAM-based FPGAs.”  In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 144-50, Oct. 2004.  Available in pdf

• M. Co and K. Skadron.  "Evaluating Trace Cache Energy-Efficiency."  Tech Report CS-2004-31, Univ. of Virginia Dept. of Computer Science, Oct. 2004.

• K. Sankaranarayanan and K. Skadron.  “Profile-Based Adaptation for Cache Decay”.  ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004.  Available in pdf.

• Y. Li, D. Brooks, Z. Hu, K. Skadron, and P. Bose.  “Understanding the Energy Efficiency of Simultaneous Multithreading.”  In Proceedings of the ACM/IEEE 2004 International Symposium on Low-Power Electronics Design (ISLPED), pp. 44-49, Aug. 2004.  Available in pdf

• J. W. Sheaffer, D. P. Luebke, and K. Skadron.  “A Flexible Simulation Framework for Graphics Architectures.”  In Proceedings of Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004.  Available in pdf [associated video, AVI]

• P. Juang, K. Skadron, M. Martonosi, Z. Hu, D. W. Clark, P. W. Diodato, and S. Kaxiras.  “Implementing Branch Predictor Decay Using Quasi-Static Memory Cells.”  ACM Transactions on Architecture and Code Optimization, 1(2):180-219, June 2004.  Available in pdf.

• D. Parikh, K. Skadron, Y. Zhang, and M. Stan.  "Power-Aware Branch Prediction, Characterization and Design."  IEEE Transactions on Computers, 53(2):168-86, Feb. 2004.

   Available in pdf (Abstract)

• Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, M. R. Stan, and K. Skadron.  “State-Preserving vs. Non-State-Preserving Leakage Control in Caches.”  In Proceedings of the 2004 Design, Automation and Test in Europe (DATE) Conference, pp. 22-27, Feb. 2004.  Available in pdf  [HotLeakage software home page]

• V. Sharma, A. Thomas, T. Abdelzaher, Z. Lu, and K. Skadron.  “Power-Aware QoS Management on Web Servers.”  In Proceedings of the 24th International Real-Time Systems Symposium, pp. 63-72, Dec. 2003.

Available in pdf  (Best student paper!)

• M. R. Stan and K. Skadron.  “Power Aware Computing,” guest editor’s introduction. IEEE Computer, 36(12), Dec. 2003.  Available in pdf

• M. Co and K. Skadron. "Evaluating the Energy Efficiency of Trace Caches." Tech Report CS-2003-19, Univ. of Virginia Dept. of Computer Science, Oct. 2003.

• Y. Li, K. Skadron, and M.R. Stan. "New Findings on Using Queue Occupancy to Integrate Runtime Power-Saving Techniques Across the Pipeline." Tech Report CS-2003-15, Univ. of Virginia Dept. of Computer Science, July 2003.

• Z. Lu, J. Lach, M.R. Stan, and K. Skadron.  "Reducing Multimedia Decode Power using Feedback Control."  In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003.

Available in pdf (Abstract)

• K. Sankaranarayanan.  "Profile-Based Adaptation for Cache Decay."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.

• D. Parikh, Y. Zhang, K. Sankaranarayanan, K. Skadron, and M. Stan.  "Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches."  In Proceedings of the Second Annual Workshop on Duplicating, Deconstructing, and Debunking in conjunction with ISCA-30, June 2003.  Available in postscript or pdf (Abstract)    [HotLeakage software home page]

• A. Thomas, "A Measurement Platform for DVS Algorithm Development and Analysis."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2003.  Available in pdf

• Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan.  "HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects."  Tech Report CS-2003-05, Univ. of Virginia Dept. of Computer Science, Mar. 2003.

Available in postscript or pdf (Abstract)  [software home page]

• D. Parikh.  "Power Aware Branch Prediction: Characterization and Design."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2003.

  Available in pdf

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.”  In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002.

Available in postscript or pdf (Abstract)

• P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi, and D.W. Clark.  "Implementing Decay Techniques using 4T Quasi-Static Memory Cells."  Computer Architecture Letters, Volume 1, Sept. 2002.

Available in postscript or pdf (Abstract)

• Z. Hu, P. Juang, K. Skadron, D. Clark, and M. Martonosi.  “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.”  In Proceedings of the 2002 International Conference on Computer Design, pp. 442-45, Sept. 2002.

Available in pdf (Abstract)

• Z. Hu, P. Juang, S. Kaxiras, P. Diodato, K. Skadron, D.W. Clark, and M. Martonosi.  “Managing Leakage for Transient Data : Decay and Quasi-Static Memory Cells.”  In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, pp. 52-55, Aug. 2002.

  Available in pdf (Abstract)

• Y. Zhang, J. Lach, K. Skadron, and M.R. Stan.  “Odd/Even Bus Invert with Two-Phase Transfer for Buses with Coupling.”  In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, pp. 80-83, Aug. 2002.

  Available in pdf

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling.”  In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002.  (best student paper!)

  Available in postscript or pdf (Abstract)

• S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.”  In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002.

Available in postscript or pdf (Abstract)

• A. Spanberger, “Designing a Dynamically Reconfigurable Cache for High Performance and Low Power.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (finalist in the 2002 SEAS Undergraduate Research and Design Symposium).

Available in pdf

• D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan.  "Power Issues Related to Branch Prediction."  In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 233-44, Feb. 2002.  (Extended version appears as TR CS-2001-25.)

Available in postscript or pdf (Abstract)

• D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan.  “Power Issues Related to Branch Prediction.” Tech Report CS-2001-25, Univ. of Virginia Dept. of Computer Science, Nov. 2001.  (Extended version of HPCA-8 paper.)

  Available in pdf (Abstract)

• Z. Hu, P. Juang, K.Skadron, M. Martonosi, and D. W. Clark. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.”  Tech Report CS-2001-24, Univ. of Virginia Dept. of Computer Science, Oct. 2001.

Available in pdf (Abstract)

Reliability

• J. W. Sheaffer.  "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007.  Available in pdf.

• J. Sheaffer, D. Luebke, and K. Skadron. “A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors.” In Proceedings of Eurographics/ACM Graphics Hardware 2007 (GH), pp. 55-64, Aug. 2007. (pdf)

• Z. Lu, W. Huang, M. Stan, K. Skadron, and J. Lach.  “Interconnect Lifetime Prediction for Reliability-Aware Systems.”  IEEE Transactions on VLSI Systems, 15(2):159-72, Feb. 2007.  (pdf)

• Z. Lu.  "Runtime Management Techniques for Power- and Temperature-aware Computing."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.  Available in pdf. 

• Z. Lu, W. Huang, M. R. Stan, K. Skadron, and J. Lach.  "Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications."  Tech Report CS-2006-23, Univ. of Virginia Dept. of Computer Science, Oct. 2006. (pdf) 

• J. W. Sheaffer, D. P. Luebke, and K. Skadron. “The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.” In Proceedings of Eurographics/ACM Graphics Hardware 2006, pp. 9-16, Sept. 2006.  (pdf)

• Z. Lu, J. Lach, M. R. Stan, and K. Skadron.  “Improved Thermal Management with Reliability Banking.”  IEEE Micro, 25(6):40-49, Nov./Dec. 2005 special issue on Reliability-Aware Microarchitectures. (pdf)

• Z. Lu, J. Lach, M. Stan, and K. Skadron. “Temperature-Aware Modeling and Banking of IC Lifetime Reliability.” Tech Report CS-2005-10, Univ. of Virginia Dept. of Computer Science, June 2005.

• Z. Lu, J. Lach, M. Stan, and K. Skadron. “Banking Chip Lifetime: Opportunities and Implementation.” In Proceedings of the Workshop on High Performance Computing Reliability Issues (HPCRI), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf

• Z. Lu, W. Huang, J. C. Lach, M. R. Stan, and K. Skadron.  “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design.”  In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 327-34, Nov. 2004.  Available in pdf

• W. Huang, Z. Lu, S. Ghosh, M. Stan, J. Lach, and K. Skadron.  “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis.”  Tech Report CS-2004-07, Univ. of Virginia Dept. of Computer Science, Jan. 2004.

Graphics Architecture and GPU Computing

• Rodinia Benchmarks Wiki

• D. Tarjan, J. Meng, and K. Skadron.  "Increasing Memory Miss Tolerance for SIMD Cores."  In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009, to appear. (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009.  (pdf)

• M. A. Guevera, C. Gregg, K. Hazelwood, and K. Skadron.  "Enabling Task Parallelism in the CUDA Scheduler."  In Proceedings of the Workshop on Programming Models for Emerging Architectures (PMEA), in conjunction with the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2009. (pdf)

• L. G. Szafaryn, K. Skadron, and J. J. Saucerman.  "Experiences Accelerating MATLAB Systems Biology Applications."  In Proceedings of the Workshop on Biomedicine in Computing: Systems, Architectures, and Circuits (BiC) 2009, in conjunction with the 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2009. (pdf)

• J. Meng and K. Skadron.  "Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs."  In Proceedings of the 23rd Annual ACM International Conference on Supercomputing (ICS), pp. 256-65, June 2009.  (pdf)

• M. Boyer, D. Tarjan, S. T. Acton, and K. Skadron.  "Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors."  In Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2009.  (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, S.-H. Lee, J. Sheaffer, and K. Skadron.  "Rodinia: A Benchmark Suite for Heterogeneous Computing."  Poster session at the 2009 ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 2009. (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron.  "A Performance Study of General Purpose Applications on Graphics Processors using CUDA."  Journal of Parallel and Distributed Computing, Elsevier, 68(10):1370-80, Oct. 2008, DOI http://dx.doi.org/10.1016/j.jpdc.2008.05.014. (UVA final preprint pdf | published pdf)

• L. Szafaryn and K. Skadron.  "Experience Porting MATLAB Systems Biology Applications to CUDA."  NVISION poster session, Aug. 2008.  (pdf)

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron.  "Experience Porting General-Purpose Applications to GPUs using CUDA."  NVISION poster session, Aug. 2008.  (pdf)

• S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach. “Accelerating Compute Intensive Applications with GPUs and FPGAs.” In Proceedings of the IEEE Symposium on Application Specific Processors (SASP), pp. 101-07, June 2008.  (pdf)

• J. Nickolls, I. Buck, M. Garland, K. Skadron.  “Scalable Parallel Programming with CUDA.”  ACM Queue, 6(2):40-53, Mar.-Apr. 2008.  DOI 10.1145/1365490.1365500 (pdf)

• M. Boyer, K. Skadron, and W. Weimer. “Automated Dynamic Analysis of CUDA Programs.” In Proceedings of the Third Workshop on Software Tools for MultiCore Systems (STMCS), in conjunction with the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Apr. 2008. (pdf)

• S. Che, J. Meng, J. W. Sheaffer, and K. Skadron.  “A Performance Study of General Purpose Applications on Graphics Processors.”  First Workshop on General Purpose Processing on Graphics Processing Units, Northeastern University, Oct. 2007.  (pdf)

• J. W. Sheaffer.  "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007.  Available in pdf.

• J. Sheaffer, D. Luebke, and K. Skadron. “A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors.” In Proceedings of Eurographics/ACM Graphics Hardware 2007 (GH), pp. 55-64, Aug. 2007. (pdf)

• K. Dale, J. W. Sheaffer, V. Vijay Kumar, D. P. Luebke, G. Humphreys, and K. Skadron.  “Applications of Small-Scale Reconfigurability to Graphics Processors.”  International Journal of Electronics, Taylor & Francis, 94(5):549-61, May 2007, DOI 10.1080/00207210701308500.  (preprint pdf)

• K. Stammetti.  "Testing the Feasibility of Running a Computationally Intensive Real-Time Traffic Simulation on a Multicore Programmable Graphics Processor."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)

• P. Sitthi-amorn, “Interactive Three-Dimensional Surface Reconstruction Using the Level Set Method on Parallel Computer Architectures." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007.

• C. Palmer. "Evaluating Reconfigurable Texture Units for Programmable Graphics Cards." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)

• A. Maier.  "GPUCT: A GPU-Accelerated CT Reconstruction System." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007.  (pdf)

• S. Cook.  "Examining Suitability of Multicore Processor Architectures for Solving Realistic Computationally Intensive Problems by Simulating Synaptic Behavior in Large Neural Networks." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)

• A. Banda.  "Implementing a Deformable Model Image Segmentation Algorithm for a Multi-Core Microprocessor Architecture." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)

• J. W. Sheaffer, D. P. Luebke, and K. Skadron. “The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.” In Proceedings of Eurographics/ACM Graphics Hardware 2006, pp. 9-16, Sept. 2006.  (pdf)

• K. Dale, J. Sheaffer, V. Vijay Kumar, D. Luebke, G. Humphreys, and K. Skadron. "Applications of Small-Scale Reconfigurability to Graphics Processors."  In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC2006), Springer-Verlag LNCS, pp. 99-108, Mar. 2006. (pdf)

• J. W. Sheaffer, K. Skadron. and D. P. Luebke. “Fine-grained Graphics Architectural Simulation with Qsilver.”  SIGGRAPH 2005 poster seesion, Aug. 2005.

• K. Dale, J. Sheaffer, V. Vijay Kumar, D. Luebke, G. Humphreys, and K. Skadron. “Applications of Small Scale Reconfigurability to Graphics Processors.” Tech Report CS-2005-11, Univ. of Virginia Dept. of Computer Science, June 2005.

• D. McWhorter, “Power Consumption Characterization of a Graphics Processing Unit.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)

• J. W. Sheaffer, K. Skadron, and D. P. Luebke.  “Studying Thermal Management for Graphics-Processor Architectures.”  In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2005.  (pdf)

• J. W. Sheaffer, D. P. Luebke, and K. Skadron.  “Temperature-Aware GPU Design.”  SIGGRAPH 2004 poster session, Aug. 2004.  (One of 5 semi-finalists for the SIGGRAPH Student Research Competition out of 53 SRC entries and 118 total posters accepted.)  Available in pdf [associated video, AVI]

• J. W. Sheaffer, D. P. Luebke, and K. Skadron.  “A Flexible Simulation Framework for Graphics Architectures.”  In Proceedings of Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004.  Available in pdf [associated video, AVI]

• N. Goodnight, G. Lewin, D. Luebke, and K. Skadron.  “A Multigrid Solver for Boundary-Value Problems Using Programmable Graphics Hardware.”  Tech Report CS-2003-03, Univ. of Virginia Dept. of Computer Science, Jan. 2003.

Available in pdf (Abstract)

MPEG

• Z. Lu, J. Lach, K. Skadron, and M. R. Stan. “Design and Implementation of an Energy Efficient Multimedia Playback System.” In Proceedings of the 40th Asilomar Conference on Signals, Systems and Computers, Oct. 2006. (pdf)

• Z. Lu, J. Lach, M.R. Stan, and K. Skadron.  "Reducing Multimedia Decode Power using Feedback Control."  In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003.

Available in pdf (Abstract)

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.”  In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002.

Available in postscript or pdf (Abstract)

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling.”  In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002.  (best student paper!)

  Available in postscript or pdf (Abstract)

Control Theory

• T. Horvath and K. Skadron.  "Multi-mode Energy Management for Multi-tier Server Clusters."  In Proceedings of the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 270-79, Oct. 2008.  (pdf |  DelayDVS and ClusterControlWare software)

• T. Horvath.  "Energy Management in Real-Time Multi-Tier Internet Services." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2008.  Available in pdf.

• T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” IEEE Transactions on Computers, 56(4):444-58, Apr. 2007.  (pdf)

• T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” Tech Report CS-2004-34, Univ. of Virginia Dept. of Computer Science, Nov. 2004.

• K. Sankaranarayanan and K. Skadron.  “Profile-Based Adaptation for Cache Decay”.  ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004.  Available in pdf.

• V. Sharma, A. Thomas, T. Abdelzaher, Z. Lu, and K. Skadron.  “Power-Aware QoS Management on Web Servers.”  In Proceedings of the 24th International Real-Time Systems Symposium, pp. 63-72, Dec. 2003.

Available in pdf  (Best student paper!)

• Z. Lu, J. Lach, M.R. Stan, and K. Skadron.  "Reducing Multimedia Decode Power using Feedback Control."  In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003. Available in pdf (Abstract)

• K. Sankaranarayanan.  "Profile-Based Adaptation for Cache Decay."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.”  In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002.

Available in postscript or pdf (Abstract)

• Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron.  “Control-Theoretic Dynamic Frequency and Voltage Scaling.”  In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002.  (best student paper!)  Available in postscript or pdf (Abstract)

• S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.”  In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002. Available in postscript or pdf (Abstract)

• K. Skadron, T. Abdelzaher, and M. Stan.  "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management."  In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 17-28, Feb. 2002.    (Extended version appears as TR CS-2001-27.)

Available in postscript or pdf  (Abstract) Erratum

• K. Skadron, T. Abdelzaher, and M.R. Stan.  “Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.”  Tech Report CS-2001-27, Univ. of Virginia Dept. of Computer Science, Nov. 2001.  (Extended version of HPCA-8 paper.)  Available in postscript or pdf (Abstract) Erratum

Branch Prediction and Instruction Fetch

• S. W. Chung and K. Skadron.  “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.”  IEEE Transactions on Computers, 57(1):7-24, Jan. 2008, DOI 10.1109/TC.2007.70770.  (pdf)

• K. Skadron and D. Tarjan.  “Predicting Branches in Computer Programs,” in The Computer Engineering Handbook, 2nd ed., CRC Press, 2007.

• M. Co, D. A. B. Weikle, and K. Skadron. "Evaluating Trace Cache Energy Efficiency." ACM Transactions on Architecture and Code Optimization (TACO), 3(4):450-76, Dec. 2006. (Abstract | pdf)

• D. Tarjan.  "Merging Path, Global and Local Indexing in Perceptron Branch Prediction."  MS thesis, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. (pdf)

• S. W. Chung and K. Skadron.  "Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction."  In Proceedings of the 11th Asia-Pacific Systems Architecture Conference (ACSAC), Sept. 2006, pp. 24-37. (pdf)

• M. Co.  "Designing Energy-Efficient Fetch Engines."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006. pdf (Abstract)

• S .W. Chung and K. Skadron. “Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction.” Tech Report CS-2006-03, Univ. of Virginia Dept. of Computer Science, Mar. 2006.  (pdf)

• M. Co, D. A. B. Weikle, and K. Skadron. “Potential for Branch Predictor Adaptation at the Program and Phase Level.” Tech Report CS-2005-19, Univ. of Virginia Dept. of Computer Science, Nov. 2005. (pdf)

• D. Tarjan and K. Skadron. “Merging Path and Gshare Indexing in Perceptron Branch Prediction.” ACM Transactions on Architecture and Code Optimization, Sept. 2005, 2(3):280-300. (pdf)

• M. Co, D. A. B. Weikle, and K. Skadron.  “A Break-Even Formulation for Evaluating Branch Predictor Energy Efficiency.”  In Proceedings of the 2005 Workshop on Complexity Effective Design (WCED) in conjunction with the 32^nd International Symposium on Computer Architecture (ISCA), June 2005.  (pdf)

• D. Tarjan and K. Skadron. “Merging Path and Gshare Indexing in Perceptron Branch Prediction.” Tech Report CS-2004-38, Univ. of Virginia Dept. of Computer Science, Dec. 2004.

• A. Malaviya, “Applying Kalman Filters to Branch Prediction.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Dec. 2004.

• M. Co and K. Skadron.  "Evaluating Trace Cache Energy-Efficiency."  Tech Report CS-2004-31, Univ. of Virginia Dept. of Computer Science, Oct. 2004.

• D. Tarjan and K. Skadron.  “Revisiting the Perceptron Predictor Again.”  Tech Report CS-2004-28, Univ. of Virginia Dept. of Computer Science, Sep. 2004.

• D. Tarjan, K. Skadron, and M.R. Stan.  “An Ahead Pipelined Alloyed Perceptron with Single Cycle Access Time.”  In Proceedings of the 2004 Workshop on Complexity Effective Design, in conjunction with the 31st International Symposium on Computer Architecture (ISCA), June 2004.  Available in pdf

• D. Parikh, K. Skadron, Y. Zhang, and M. Stan.  "Power-Aware Branch Prediction, Characterization and Design."  IEEE Transactions on Computers, 53(2):168-86, Feb. 2004.

   Available in pdf (Abstract)

• M. Co and K. Skadron. "Evaluating the Energy Efficiency of Trace Caches." Tech Report CS-2003-19, Univ. of Virginia Dept. of Computer Science, Oct. 2003.

• K. R. Hirst, J. W. Haskins Jr., K. Skadron. "dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading: Extended Results." Tech Report CS-2003-18, Univ. of Virginia Dept. of Computer Science, Oct. 2003.

  (Extended version of Jan. 2004 IEE Proceedings on Computers and Digital Techniques paper.)

• Z. Lu, J. Lach, M. Stan, and K. Skadron.  “Alloyed Branch History: Combining Global and Local Branch History for Robust Performance,” International Journal of Parallel Programming, Kluwer, 31(2):137-77, Apr. 2003.  Available in pdf (Abstract)

• D. Parikh.  "Power Aware Branch Prediction: Characterization and Design."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2003.

  Available in pdf

• Z. Hu, P. Juang, K. Skadron, D. Clark, and M. Martonosi.  “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.”  In Proceedings of the 2002 International Conference on Computer Design, pp. 442-45, Sept. 2002. Available in pdf (Abstract)

• Z. Hu, P. Juang, S. Kaxiras, P. Diodato, K. Skadron, D.W. Clark, and M. Martonosi.  “Managing Leakage for Transient Data : Decay and Quasi-Static Memory Cells.”  In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, Aug. 2002.

Available in pdf (Abstract)

• Z. Lu, J. Lach, M.R. Stan, and K. Skadron. “Alloyed Branch History: Combining Global and Local Branch History for Robust Performance,”  Tech Report CS-2002-21, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract) -- superseded by a paper with the same title appearing in the International Journal of Parallel Programming, Kluwer, volume 31, number 2, Apr. 2003, see above.

• D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan.  "Power Issues Related to Branch Prediction."  In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 233-44, Feb. 2002.   (Extended version appears as TR CS-2001-25.)

Available in postscript or pdf (Abstract)

• K. Skadron.  “Predicting Branches in Computer Programs,” in The Computer Engineering Handbook, CRC Press, 2002.

• D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan.  “Power Issues Related to Branch Prediction.” Tech Report CS-2001-25, Univ. of Virginia Dept. of Computer Science, Nov. 2001.  (Extended version of HPCA-8 paper.) Available in pdf (Abstract)

• Z. Hu, P. Juang, K.Skadron, M. Martonosi, and D. W. Clark. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.”  Tech Report CS-2001-24, Univ. of Virginia Dept. of Computer Science, Oct. 2001. Available in pdf (Abstract)

• M. Co and K. Skadron.  "The Effects of Context Switching on Branch Predictor Performance."  In Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 77-84, Nov. 2001.

Available in postscript or pdf (Abstract)

• K. Sankaranarayanan and K. Skadron.  “A Scheme for Selective Squash and Re-issue for Single-Sided Branch Hammocks.”  In Proceedings of the Work-in-Progress Session at the 2001 International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001.   Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 4-5, Oct. 2001. Available in pdf

• K. Sankaranarayanan and K. Skadron.  "A Scheme for Selective Squash and Re-issue for Single-Sided Branch Hammocks."  Tech Report CS-2001-14, Univ. of Virginia Dept. of Computer Science, July, 2001. Available in pdf (Abstract)

• M. Co.  "The Effects of Context Switching on Branch Predictor Performance."  MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2001.

Available in postscript

• J.C. Ablutz.  "Analyzing and Improving Alloyed Branch Predictor Performance."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001.

Available in Word

• S. Kelley.  "Branch and Confidence Prediction with Perceptrons."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001.

Available in Word

• K. Skadron, M. Martonosi, and D.W. Clark. "A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions." In Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, pp. 199-206, Oct. 2000. Available in postscriptor pdf (Abstract)

• P. Juang.  "Classification-based Hybrid Branch Prediction."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science; also Dept. of Computer Science Tech. Report CS-2000-15; Mar. 2000. Available in postscript (Abstract)

• A.V. Lanning.  "Pipelined Branch Prediction: Characterizing Wrong-History Misprediction."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science; Apr. 2000.

Available in Word

• K. Skadron, M. Martonosi, and D.W. Clark.  "Speculative Updates of Local and Global Branch History: A Quantitative Analysis."  Journal of Instruction-Level Parallelism, vol. 2, Jan. 2000(http://www.jilp.org/vol2).

Available in postscript (Abstract)

• K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark.  "Branch Prediction, Instruction-Window Size, and Cache Size: Performance Tradeoffs and Simulation Techniques."  IEEE Transactions on Computers, 48(11):1260-81, Nov. 1999.

Available in pdf (Abstract)

• K. Skadron, M. Martonosi, and D.W. Clark.  "Alloying Global and Local Branch History: A Robust Solution to Wrong-History Mispredictions."  Tech Report TR-606-99, Princeton Dept. of Computer Science, Oct. 1999.

Available in postscript (Abstract)

• K. Skadron. "Characterizing and Removing Branch Mispredictions." PhD dissertation, Princeton Univ.; also Tech. Report TR-604-99; June 1999.

Available in gzip'd postscript or PDF.  (Abstract)

• K. Skadron, M. Martonosi, and D.W. Clark.  "Alloying Global and Local Branch History: Taxonomy, Performance, and Analysis."  Tech Report TR-594-99, Princeton Dept. of Computer Science, Jan. 1999.

Available in postscript (Abstract)

• K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark.  "Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms."  In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp. 259-71, December 1998.

Available in postscript or pdf (Abstract)

• P.S. Ahuja, K. Skadron, M. Martonosi, and D.W. Clark.  "Multipath Execution: Opportunities and Limits."  In Proceedings of the 1998 International Conference on Supercomputing, pp. 101-08, July 1998.

Available in postscript or pdf (Abstract)

Caching and Write Buffers

• D. Tarjan, J. Meng, and K. Skadron.  "Increasing Memory Miss Tolerance for SIMD Cores."  In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009, to appear. (pdf)

• J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.”  In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)

• K. Sankaranarayanan and K. Skadron.  “Profile-Based Adaptation for Cache Decay”.  ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004.  Available in pdf.

• K. Sankaranarayanan.  "Profile-Based Adaptation for Cache Decay."  MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.

• S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.”  In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002.

Available in postscript or pdf (Abstract)

• A. Spanberger, “Designing a Dynamically Reconfigurable Cache for High Performance and Low Power.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (finalist in the 2002 SEAS Undergraduate Research and Design Symposium).

Available in pdf

• M. Ziegler, A. Spanberger, G. Pai, M. Stan, and K. Skadron.  “Dynamic Way Allocation for High Performance, Low Power Caches.” In Proceedings of the Work-in-Progress Session at the 2001 International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001.  Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 14-15, Oct. 2001.

Available in pdf

• D.A.B. Weikle.  "A Framework for the Analysis of Caching Systems."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001.

Available in postscript or pdf (Abstract)

• D.A.B. Weikle, K. Skadron, S.A. McKee, and W.A. Wulf.  "TSpec: A Notation for Describing Memory Reference Traces."  Tech Report CS-2000-23, Univ. of Virginia Dept. of Computer Science, Aug. 2000.

Available in postscript (Abstract)

• D.A.B. Weikle, K. Skadron, S.A. McKee, and W.A. Wulf.  "Caches As Filters:


A Unifying Model for Memory Hierarchy Analysis."  Tech Report CS-2000-16, Univ. of Virginia Dept. of Computer Science, June, 2000. Available in postscript (Abstract)

• D.A.B. Weikle, S.A. McKee, K. Skadron, and W.A. Wulf. "Caches as Filters: A Framework for the Analysis of Caching Systems." In Proceedings of the Third Grace Hopper Celebration of Women in Computing Conference - 2000, Sept. 2000.

Available in pdf (Abstract)

• K. Skadron and D.W. Clark.  "Design Issues and Tradeoffs for Write Buffers."  In Proceedings of the Third International Symposium on High-Performance Computer Architecture, pp. 144-55, February 1997.

Available in postscript or pdf (Abstract)

• K. Skadron and D.W. Clark.  "Measuring the Effects of Retirement and Load-Service Policies on Write Buffer Performance."  In Proceedings of the 1996 Workshop on Performance Analysis and its Impact on Design (PAID), March 1996.

• An index of papers pertaining to write buffers

Performance Tradeoffs and Simulation Methodology

• Rodinia Benchmarks Wiki
• Genetically Programmed Response Surfaces Toolkit
• AmberBBV, for generating basic block vectors (e.g. for use with SimPoint) from Amber traces (part of the CHUD tools).

• Qsilver home page

• MRRL home page

 

• Hydrascalar home page

• S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009.  (pdf)

• H. Cook and K. Skadron. “Predictive Design Space Exploration Using Genetically Programmed Response Surfaces.” In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf | Genetically Programmed Response Surfaces Toolkit software)

• H. Cook and K. Skadron.  "Genetically Programmed Response Surfaces for Efficient Design Space Exploration" Univ. of Virginia Dept. of Computer Science Tech. Report CS-2007-12, Aug. 2007. (pdf)

• H. Cook.  "Optimizing Chip Multiprocessor Designs Using Genetically Programmed Response Surfaces" Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007.  (Awarded first place in the 2007 UVA SEAS Undergraduate Research and Design Symposium)  (pdf)

• J. Meng, H. Cook, K. Skadron, and D. A. B. Weikle. “Comparing Doom 3, WarCraft III, PBRT, and MESA Using Micro-architecturally Independent Characteristics.” Tech Report CS-2007-04, Univ. of Virginia Dept. of Computer Science, Feb. 2007.  (pdf)

• P. Sitthi-Amorn, D. A. B. Weikle, and K. Skadron. “Exploring the Impact of Normality and Significance Te sts in Architecture Experiments.” In Proceedings of the 2006 Workshop on Modeling, Benchmarking and Simulation, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA ), June 2006. (pdf)

• Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. Latch­Mux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005.  (pdf)

• J.W. Haskins, Jr. and K. Skadron. “Accelerated Warmup for Sampled Microarchitecture Simulation.” ACM Transactions on Architecture and Compiler Optimization, 2(1):78-108, Mar. 2005.  (pdf)

• K.-J. Lee and K. Skadron. “Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors.” In Proceedings of the Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with the 2005 International Parallel and Distributed Processing Symposium, Apr. 2005.  Available in pdf   [Presentation slides pdf]

• Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.

• S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for Temperature-Aware Microarchitecture Research.” In the 2005 Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf

• J. W. Sheaffer, D. P. Luebke, and K. Skadron.  “A Flexible Simulation Framework for Graphics Architectures.”  In Proceedings of the Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004.  Available in pdf [associated video, AVI] [Qsilver software home page]

• K. Skadron, M. Martonosi, D. I. August, M. D. Hill, D. J. Lilja, and V. S. Pai.  "Challenges in Computer Architecture Evaluation."  IEEE Computer, Aug. 2003.

Available in pdf (Abstract)

• J. W. Haskins, Jr.  "Accelerating Sampled Microarchitecture Simulation: Rapid Warm Up for Simulated Hardware State."  PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2003.  Available in pdf

• Y. Zilbergleyt, "Finding and Characterizing New Benchmarks for Computer Architecture Research."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2003.  Available in pdf

• J.W. Haskins, Jr. and K. Skadron.  “Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation.”   In Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 195-203, Mar. 2003. Available in postscript or pdf (Abstract)  [software home page]

• J. W. Haskins, Jr. and K. Skadron.  “Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation.”   Tech Report CS-2002-19, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract) -- superseded by a paper with the same title appearing in Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, Mar. 2003, see above.

• E. Bauer, “Examination of a Novel Method of Emulating System Calls in Microprocessor Simulators.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002.

Available in Word

• J. W. Haskins, Jr., A. J. KleinOsowski, K. Skadron, and D. J. Lilja.  "Techniques for Accurate, Accelerated Processor Simulation: Analysis of Reduced Inputs and Sampling."  Tech Report CS-2002-01, Univ. of Virginia Dept. of Computer Science, Jan. 2002.

Available in postscript (Abstract)

• J.W. Haskins and K. Skadron.  "Minimal Subset Evaluation: Rapid Warm-up for Simulated Hardware State."  In Proceedings of the 2001 International Conference on Computer Design, pp. 32-39, Sept. 2001.

Available in pdf (Abstract)

• S.K. Chan.  "Building and Distributing a Next-Generation Benchmark Suite for Computer Research."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001.

Available in Word  (supporting data)

• K. Skadron and P.S. Ahuja.  "HydraScalar: A Multipath-Capable Simulator."  In the Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 65-70, Jan. 2001.

Available in postscript or pdf (Abstract)  [software home page]

• K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark.  "Branch Prediction, Instruction-Window Size, and Cache Size: Performance Tradeoffs and Simulation Techniques."  IEEE Transactions on Computers, 48(11):1260-81, Nov. 1999.

Available in pdf (Abstract)

• K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark, "Selecting a Single, Representative Sample for Accurate Simulation of SPECint Benchmarks."  Tech Report TR-595-99, Princeton Dept. of Computer Science, Jan. 1999.

Available in gzip'd postscript or pdf (Abstract)

Miscellaneous

• M. Guevara and C. Gregg. “Fault-tolerant, Real-time Reconfigurable Prefix Adder.” Tech. Report CS-2009-09, Univ. of Virginia Dept. of Computer Science, Sep 2009. (pdf)

• D. Grosvenor.  "Detection and Tracking of Human Subjects."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2009. (pdf)

• J. Meng, D. A. B. Weikle, G. Humphreys, and K. Skadron.  “An Approach on Hardware Design for Computational Photography.”  Tech. Report CS-2007-15, Univ. of Virginia Dept. of Computer Science, Nov. 2007.  (pdf)

• A. Mukherjee, “Development of Visualization Tools for . Mukherjee and K. Skadron.  “Measuring Parameter Variation on an FPGA Using Ring Oscillators.”  Tech Report CS-2006-16, Univ. of Virginia Dept. of Computer Science, June 2006. (pdf)

• A. Mukherjee, “Development of Visualization Tools for Out-of-Order Execution Simulators.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005.

  (pdf) 

• P. Dadvar, “Security Threats of Power and Thermal Control Intefaces.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005.  (pdf)

• P. Dadvar and K. Skadron.  “Potential Thermal Security Risks.”  In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 21), pp. 229-34, Mar. 2005.  Available in pdf

• K. Hirst.  "Hardware Support for SDT: The Use of Hardware Counters for Hot Spot Detection in Strata."  MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2002.

Available in pdf

• M.R. Stan and K. Skadron.  “Teaching Processor Architecture with a VLSI Perspective.”  In Proceedings of the Workshop on Computer Architecture Education (WCAE), in conjunction with ISCA-29, May 2002.

• J. Erdman, “Lighting Integrated Technology: Improvements to a Dynamic Theater System.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (featured in the University Undergraduate Research Symposium).

• P. Lamanna, “Adaptive Security Policies Enforced by Software Dynamic Translation.”  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002.

Available in pdf

• K. Skadron.  "A Microprocessor Survey Course for Learning Advanced Computer Architecture."  In Proceedings of the 2002 SIGCSE Symposium, pp. 152-56, Feb.-Mar. 2002.

Available in postscript or pdf (Abstract)

• K. Skadron, M. Humphrey, B. Huang, E. Hilton, J. Luo, and P. Allaire. "The Use of Mini-Vector Instructions for Implementing High-Speed Feedback Controllers on General-Purpose Computers."   In Proceedings of the 3rd Workshop on Media and Stream Processors, in conjunction with MICRO-34, Dec. 2001. Available in postscript or pdf (Abstract)

• K. Skadron, M. Humphrey, B. Huang, E. Hilton, J. Luo, and P. Allaire.  “Supporting Higher-Order Controllers for Magnetic Bearings in a High-Speed, Real-Time Platform Using General-Purpose Computers.”  In Proceedings of the 2001 International Symposium on Magnetic Suspension Technology, Oct. 2001.

Available in pdf (Abstract)

• K. Scott, K. Skadron, and J. W. Davidson.  “Low-Overhead Software Dynamic Translation.” Tech Report CS-2001-18, Univ. of Virginia Dept. of Computer Science, Sept. 2001.

Available in pdf (Abstract)

• J. Miranda.  "The Usage of Compiler Optimization by Programmers:  A Sociological Study of the Extent of Their Use and the Rationales Behind this Usage."  Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001.

Available in Word

• K. Scott and K. Skadron.  "BLP: Applying ILP Techniques to Bytecode Execution."  In Proceedings of the Second Annual Workshop on Hardware Support for Objects and Microarchitectures for Java, in conjunction with ICCD 2000, Sept. 2000.

Available in postscript or pdf (Abstract)

• K. Skadron.  "A Microprocessor Survey Course: Exploring Advanced Computer Architecture in Practice."  In Proc. of the Workshop on Computer Architecture Education, in conjunction with ISCA-27, June 2000.

Available in postscript or pdf (Abstract)

• B.S. White and K. Skadron.  "Path-Based Target Prediction for File System

Prefetching."  Tech Report CS-2000-06, Univ. of Virginia Dept. of Computer Science, June, 2000. Available in postscript (Abstract)

• K. Skadron, S.A. Watson, and K.H. Mueller.  "A Study of Spectral Effects Using Synthetic Radiography."  Los Alamos Unclassified Report LAUR 944247, Los Alamos National Laboratory, Dec. 1994. (Abstract)

Software Releases

• Rodinia Benchmarks Wiki
• DelayDVS and ClusterControlWare - software for power management in multi-tier servers
• Genetically Programmed Response Surfaces Toolkit

• HotSpot

• HotLeakage

• AmberBBV, for generating basic block vectors (e.g. for use with SimPoint) from Amber traces (part of the CHUD tools).

• Qsilver

• MRRL tools

• HydraScalar